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參數(shù)資料
| 型號： | XRT7302 |
| 廠商： | Exar Corporation |
| 英文描述： | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| 中文描述： | 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元） |
| 文件頁數(shù)： | 46/62頁 |
| 文件大?。?/td> | 715K |
| 代理商： | XRT7302 |
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
á
PRELIMINARY
REV. 1.1.6
42
RxClk(n) is the Recovered Clock signal from the in-
coming Received line signal. As a result, these clock
signals are typically 34.368 MHz for E3 applications,
44.736 MHz for DS3 applications and 51.84 MHz for
SONET STS-1 applications.
In general, if a given channel received a positive-po-
larity pulse in the incoming line signal via the RTIP(n)
and RRing(n) input pins, then the channel pulses its
corresponding RPOS(n) output pin "High". If the
channel received a negative-polarity pulse in the in-
coming line signal via the RTIP(n) and RRing(n) input
pins, then the Channel(n) pulses its corresponding
RNEG(n) output pin "High".
Inverting the RxClk(n) outputs
Both channels can invert the RxClk(n) signals with re-
spect to the delivery of the RPOS(n) and RNEG(n)
output data to the Receiving Terminal Equipment.
This feature may be useful for those customers
whose Receiving Terminal Equipment is designed
such that the RPOS(n) and RNEG(n) data must be
sampled on the rising edge of RxClk(n). Figure 24 il-
lustrates the behavior of the RPOS(n), RNEG(n) and
RxClk(n) signals when the RxClk(n) signal has been
inverted.
a. Operating in the Hardware Mode
Setting the RxClkINV pin “High” results in all chan-
nels of the XRT7302 to output the recovered data on
RPOS(n) and RNEG(n) on the falling edge of Rx-
Clk(n). Setting this pin “Low” results in the recovered
data on RPOS(n) and RNEG(n) to output on the ris-
ing edge of RxClk(n).
b. Operating in the HOST Mode
In order to configure a channel of the XRT7302 to in-
vert the RxClk(n) output signal, the XRT7302 must be
operating in the HOST Mode.
To invert RxClk(n) associated with Channel(n), write a
"1" into the RxClk(n)INV bit-field in Command Regis-
ter CR-3 as illustrated below.
F
IGURE
23. H
OW
THE
XRT7302
OUTPUTS
DATA
ON
THE
RPOS
AND
RNEG
OUTPUT
PINS
RxClk
RPOS
RNEG
F
IGURE
24. T
HE
B
EHAVIOR
OF
THE
RPOS, RNEG
AND
R
X
C
LK
SIGNALS
WHEN
R
X
C
LK
IS
INVERTED
RxClk
RPOS
RNEG
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