參數(shù)資料
型號(hào)： XRT7302
廠商： Exar Corporation
英文描述： 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線(xiàn)接口單元)
中文描述： 2頻道E3/DS3/STS-1線(xiàn)路接口單元（2通道E3/DS3/STS-1線(xiàn)接口單元）
文件頁(yè)數(shù)： 3/62頁(yè)
文件大小： 715K
代理商： XRT7302
á
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.6
I
TABLE OF CONTENTS
General description ........................................................................................................... 1
FEATURES ................................................................................................................................................ 1
APPLICATIONS ......................................................................................................................................... 1
XRT7302 BLOCK DIAGRAM ..................................................................................................................... 1
TRANSMIT INTERFACE CHARACTERISTICS ........................................................................................ 2
RECEIVE INTERFACE CHARACTERISTICS ........................................................................................... 2
PIN OUT OF THE XRT7302 ...................................................................................................................... 2
.................................................................................TABLE OF CONTENTS I
Pin descriptions ................................................................................................................. 3
ELECTRICAL CHARACTERISTICS ................................................................................. 14
ABSOLUTE MAXIMUM RATINGS ................................................................................................... 14
Figure 1.Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel shown) ...... 16
Figure 2.Timing Diagram of the Transmit Terminal Input Interface ................................................................ 16
Figure 3.Timing Diagram of the Receive Terminal Output Interface .............................................................. 16
Figure 4.Microprocessor Serial Interface Data Structure ............................................................................... 20
Figure 5.Timing Diagram for the Microprocessor Serial Interface .................................................................. 21
SYSTEM DESCRIPTION ................................................................................................... 22
THE TRANSMIT SECTION - CHANNELS 0 AND 1 ................................................................................ 22
THE RECEIVE SECTION - CHANNELS 0 AND 1 ................................................................................... 22
THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 22
Table 1:Role of Microprocessor Serial Interface pins when the XRT7302 is operating in the Hardware Mode ..
22
Figure 6.Functional Block Diagram of the XRT7302 ...................................................................................... 23
1.0 SELECTING THE DATA RATE ......................................................................................................... 23
1.1 C
ONFIGURING
C
HANNEL
(
N
) ............................................................................................................ 23
Table 2:Addresses and Bit Formats of XRT7302 Command Registers ......................................................... 24
Table 3:Selecting the Data Rate for Channel(n) of the XRT7302, via the E3_Ch(n) and STS-1/DS3_Ch(n) input
pins (Hardware Mode) ....................................................................................................................... 24
COMMAND REGISTER CR4-(N) .................................................................................................... 25
Table 4:Selecting the Data Rate for Channel(n) of the XRT7302 via the STS-1/DS3_Ch(n) and the E3_Ch(n)
bit-fields in the Appropriate Command Register (HOST Mode) ........................................................ 25
2.0 THE TRANSMIT SECTION ............................................................................................................... 25
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
......................................................................................................... 25
Accepting Dual-Rail Data from the Terminal Equipment ................................................................... 25
Figure 7. The typical interface for Data Transmission in Dual-Rail Format from the Transmitting Terminal Equip-
ment to the Transmit Section of a channel of the XRT7302 ............................................................. 26
Figure 8.How the XRT7302 Samples the data on the TPData and TNData input pins .................................. 26
Configure Channel(n) to accept Single-Rail Data from the Terminal Equipment .............................. 26
COMMAND REGISTER CR1-(N) ..................................................................................................... 26
Figure 9.The Behavior of the TPData and TxClk Input Signals while the Transmit Logic Block is Accepting Sin-
gle-Rail Data from the Terminal Equipment ..................................................................................... 27
2.2 T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IRCUITRY
................................................................. 27
2.3 T
HE
HDB3/B3ZS E
NCODER
B
LOCK
............................................................................................... 27
B3ZS Encoding .................................................................................................................................. 27
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