XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
7
AE4
INT
O
Interrupt Request Output:
This open-drain, active-”Low” output signal will be asserted when the UNI/Framer
is requesting interrupt service from the local microprocessor. This output pin
should typically be connected to the “Interrupt Request” input of the local micro-
processor.
AC4
AD3
AF3
PTYPE0
PTYPE1
PTYPE2
I
Microprocessor Type Select Input:
These three input pins permit the user to configure the Microprocessor Interface
block to readily support a wide variety of Microprocessor Interfaces. The relation-
ship between the settings of these input pins and the corresponding Microproces-
sor Interface configuration is presented below.
PTYPE[2:0] Microprocessor Interface Mode
000 Asynchronous Intel
001 Asynchronous Motorola
010 Intel X86
011 Intel I960, Motorola MPC860
100 IDT3051/52 (MIPS)
101 IBM Power PC
Read Data Strobe (Intel Mode):
If the microprocessor interface is operating in the Intel Mode, then this input will
function as the RD (READ Strobe) input signal from the local
μ
P
. Once this
active-”Low” signal is asserted, then the UNI/Framer will place the contents of
the addressed registers (within the UNI/Framer IC) on the Microprocessor Data
Bus (D[7:0]). When this signal is negated, the Data Bus will be tri-stated.
Data Strobe (Motorola Mode):
If the microprocessor interface is operating in the Motorola mode, then this pin will
function as the active-”Low” DS (DATA Strobe) signal.
READY or DTACK:
This active-”Low” output pin will function as the READY output, when the micro-
processor interface is running in the Intel Mode; and will function as the DTACK
output, when the microprocessor interface is running in the Motorola Mode.
Intel Mode—READY Output.
When the UNI negates this output pin (e.g., toggles it “Low”), it indicates to the
μ
P that the current READ or WRITE cycle is to be extended until this signal is
asserted (e.g., toggled “High”).
Motorola Mode:—DTACK (Data Transfer Acknowledge) Output.
The UNI Framer will assert this pin in order to inform the local microprocessor
that the present READ or WRITE cycle is nearly complete. If the UNI/Framer
requires that the current READ or WRITE cycle be extended, then the UNI/
Framer will delay its assertion of this signal. The 68000 family of
μ
Ps requires
this signal from its peripheral devices in order to quickly and properly complete a
READ or WRITE cycle.
Reset Input:
When this active-”Low” signal is asserted, the UNI/Framer will be asynchro-
nously reset. When this occurs, all outputs will be “tri-stated” and all on-chip reg-
isters will be reset to their default values.
AF1
RD_DS
I
AD1
RDY_DTACK
O
V2
Reset
I
AD5
μ
PClk
I
Microprocessor Interface Clock Input
This clock input signal is used for synchronous/burst/DMA data transfer opera-
tions. This clock can be running up to 33MHz.
PIN DESCRIPTION
P
IN
#
N
AME
T
YPE
D
ESCRIPTION