XRT75L00
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
43
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL
0x08
Reserved
ADDRESS
(HEX)
TYPE
BIT
LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
0x20
R/W
D0
INTEN
Bit 0 = INTEN Writing a “1” to this bit enables the
interrupts.
0
0x21
Read
Only
D0
INTST
Bit 0 = INTST bit is set to “1” if an interrupt service is
required. The source level interrupt status register is
read to determine the cause of interrupt.
0
0x22 -
0x2F
Reserved
0x30
Reset
Upon
Read
D[7:0]
PRBSmsb
PRBS error counter MSB [15:8]
0x31
Reset
Upon
Read
D[7:0]
PRBSlsb
PRBS error counter LSB [7:0]
0x32-
0x37
Reserved
0x38
Read
Only
D[7:0]
PRBShold
PRBS Holding Register
0x39-
0x3D
Reserved
0x3E
Read
Only
D[7:0]
Chip_id
This read only register contains device id.
01110001
0x3F
Read
Only
D[7:0]
Chip_version This read only register contains chip version number
00000001
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)