PIN DESCRIPTIONS (BY FUNCTION
參數(shù)資料
型號: XRT75L00IV
廠商: Exar Corporation
文件頁數(shù): 47/50頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 SGL 52TQFP
標準包裝: 96
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 1/1
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應商設備封裝: 52-TQFP(10x10)
包裝: 托盤
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
4
PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
PIN #SIGNAL NAME
TYPE
DESCRIPTION
4TxON
I
Transmitter ON Input
Setting this input pin "High" turns on the Transmitter.
NOTES:
1.
Even when the XRT75L00 is configured in HOST mode, this pin still
controls the TTIP and TRING outputs
2.
When the Transmitter is turned off either in Host or Hardware
mode,the TTIP and TRING outputs are Tri-stated.
3.
This pin is internally pulled down
46
TxClk
I
Transmit Clock Input for TPData and TNData
The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm.
The duty cycle can be 30%-70%.
The XRT75L00 samples the TPData and TNData pins on the falling or rising
edge of TxClk signal based on the status of TxClkINV pin (in Hardware mode)
or the status of the bit in the Channel Register (in HOST mode).
26
TxClkINV/
SClk
I
Transmit Clock Invert or Serial Clock Input:
Function of this depends on whether the XRT75L00 is configured to operate in
Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures the Transmitter to
sample the TPData and TNData data on the rising edge of the TxClk.
NOTE: If the XRT75L00 is configured in HOST mode, this pin functions as SClk
input pin (please refer to the pin description for Microprocessor
interface).
48
TNData
I
Transmit Negative Data Input
If the XRT75L00 is configured in Dual-rail mode, this pin is sampled on the fall-
ing or rising edge of TxClk based on the status of the TClkINV pin (in Hardware
mode) or the status of the control bit in the Channel Register (in HOST mode).
NOTES:
1.
This input pin is ignored and should be tied to GND if the Transmitter
Section is configured to accept Single-Rail data from the Terminal
Equipment.
47
TPData
I
Transmit Positive Data Input
The XRT75L00 samples this pin on the falling or rising edge of TxClk based on
the status of the TClkINV pin (in Hardware mode) or the status of the control bit
in the Channel Register (in HOST mode).
50
TTIP
O
Transmit TTIP Output
The XRT75L00 uses this pin along with TRING to transmit a bipolar signal to
the line using a 1:1 transformer.
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相關代理商/技術參數(shù)
參數(shù)描述
XRT75L00IV-F 功能描述:外圍驅動器與原件 - PCI Sngl Chip LIU DS3/E3 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75L00IVTR 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L00IVTR-F 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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