參數(shù)資料
型號(hào): XRT75L04DIV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PQFP176
封裝: 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
文件頁(yè)數(shù): 2/98頁(yè)
文件大?。?/td> 536K
代理商: XRT75L04DIV
XRT75L04D
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
á
REV. 1.0.1
2
TRANSMIT INTERFACE CHARACTERISTICS
Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
Integrated Pulse Shaping Circuit.
Built-in B3ZS/HDB3 Encoder (which can be disabled).
Accepts Transmit Clock with duty cycle of 30%-70%.
Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications.
Generates pulses that comply with the DSX-3 pulse template, as specified in Telcordia GR-499
-CORE
and
ANSI T1.102_1993.
Generates pulses that comply with the STSX-1 pulse template, as specified in Telcordia GR-253-CORE.
Transmitters can be turned off to support redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery.
Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications.
Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications.
Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms.
Built-in B3ZS/HDB3 Decoder (which can be disabled).
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75L04D
HOST/HW
STS-1/DS3_(n)
E3_(n)
REQEN_(n)
RTIP_(n)
RRing_(n)
SR/DR
LLB_(n)
XRT75L04D
RLB_(n)
RLOS_(n)
JATx/Rx
TPData_(n)
TNData_(n)
TxClk_(n)
TAOS_(n)
TxLEV_(n)
TxON_(n)
Channel 3
Channel 0
Channel 1..2
Notes: 1. (n) = 0, 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in "Host" Mode and redefined in the "Hardware" Mode.
Device
Monitor
MTIP_(n)
MRing_(n)
DMO_(n)
Timing
Control
TTIP_(n)
TRing_(n)
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
RLOL_(n)
RxON
RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)/
LCV_(n)
Tx
Control
Jitter
Attenuator
MUX
Line
Driver
Invert
Remote
LoopBack
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
Jitter
Attenuator
Serial
Processor
Interface
Local
LoopBack
Clock & Data
Recovery
Clock
Synthesizer
E3Clk,DS3Clk,
STS-1Clk
RESET
CS
SClk
INT
SDO
SDI
CLKOUT
相關(guān)PDF資料
PDF描述
XRT75L04 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L04IV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L06DIB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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XRT75L04IV 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4CH E3/DS3/STS1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray