á
REV. 1.0.1
XRT75L04D
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
4
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0E ................................................................. 83
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
16...................................................................83
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- (C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07 .................................................. 83
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F ..................................................... 83
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17...................................................... 83
9.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR
TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ........................ 84
9.8.2.1 SOME NOTES PRIOR TO STARTING THIS DISCUSSION: ............................................................................ 84
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07.................................................... 84
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F ............................................... 84
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17................................................ 84
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07.................................................... 84
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F .............................................. 84
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17............................................... 84
9.8.2.2 OUR PRE-PROCESSING RECOMMENDATIONS ............................................................................................ 85
F
IGURE
58. I
LLUSTRATION
OF
MINOR PATTERN P1........................................................................................................................... 85
F
IGURE
59. I
LLUSTRATION
OF
MINOR PATTERN P2........................................................................................................................... 86
F
IGURE
60. I
LLUSTRATION
OF
P
ROCEDURE
WHICH
IS
USED
TO
S
YNTHESIZE
MAJOR PATTERN A ........................................................ 86
F
IGURE
61. I
LLUSTRATION
OF
MINOR PATTERN P3........................................................................................................................... 87
F
IGURE
62. I
LLUSTRATION
OF
P
ROCEDURE
WHICH
IS
USED
TO
S
YNTHESIZE
PATTERN B..................................................................... 87
9.8.3 HOW DOES THE LIU PERMIT THE USER TO COMPLY WITH THE SONET APS RECOVERY TIME REQUIREMENTS
OF 50MS (PER TELCORDIA GR-253-CORE) ............................................................................................................ 88
F
IGURE
63. I
LLUSTRATION
OF
THE
SUPER PATTERN
WHICH
IS
OUTPUT
VIA
THE
"OC-N
TO
DS3" M
APPER
IC ..................................... 88
F
IGURE
64. S
IMPLE
I
LLUSTRATION
OF
THE
LIU
BEING
USED
IN
A
SONET D
E
-S
YNCHRONIZER
" A
PPLICATION
........................................... 88
T
ABLE
24: M
EASURED
APS R
ECOVERY
T
IME
AS
A
FUNCTION
OF
DS3
PPM
OFFSET
............................................................................... 89
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07.................................................... 89
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F .............................................. 89
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17............................................... 89
9.8.4 HOW SHOULD ONE CONFIGURE THE LIU, IF ONE NEEDS TO SUPPORT "DAISY-CHAIN" TESTING AT THE END
CUSTOMER'S SITE..................................................................................................................................................... 90
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07.................................................... 90
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F ..................................................... 90
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17...................................................... 90
APPENDIX B................................................................................................................................. 91
T
ABLE
25: TRANSFORMER RECOMMENDATIONS......................................................................................................................... 91
T
ABLE
26: T
RANSFORMER
D
ETAILS
....................................................................................................................................................... 91
ORDERING INFORMATION ..................................................................................................................93
P
ACKAGE
D
IMENSIONS
- 176
PIN
PACKAGE
................................................................................................................. 93
R
EVISIONS
..................................................................................................................................................................94