參數(shù)資料
型號： XRT75L04DIV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PQFP176
封裝： 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
文件頁數(shù)： 6/98頁
文件大?。?/td> 536K
代理商： XRT75L04DIV
XRT75L04D
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
á
REV. 1.0.1
3
F
IGURE
36. A
N
I
LLUSTRATION
OF
T
ELCORDIA
GR-253-CORE'
S
R
ECOMMENDATION
ON
HOW
MAP
DS3
DATA
INTO
AN
STS-1 SPE......... 60
F
IGURE
37. A S
IMPLIFIED
"B
IT
-O
RIENTED
" V
ERSION
OF
T
ELCORDIA
GR-253-CORE'
S
R
ECOMMENDATION
ON
HOW
TO
MAP
DS3
DATA
INTO
AN
STS-1 SPE.......................................................................................................................................................................... 60
9.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS......................................... 61
9.2.2.1 T
HE
I
DEAL
C
ASE
FOR
M
APPING
DS3
DATA
INTO
AN
STS-1 S
IGNAL
(
E
.
G
.,
WITH
NO
F
REQUENCY
O
FFSETS
) ............ 62
F
IGURE
38. A S
IMPLE
I
LLUSTRATION
OF
A
DS3 D
ATA
-S
TREAM
BEING
M
APPED
INTO
AN
STS-1 SPE,
VIA
A
PTE .................................... 62
9.2.2.2 T
HE
44.736M
BPS
+ 1
PPM
C
ASE
........................................................................................................................... 63
F
IGURE
39. A
N
I
LLUSTRATION
OF
THE
STS-1 SPE
TRAFFIC
THAT
WILL
BE
GENERATED
BY
THE
"S
OURCE
" PTE,
WHEN
MAPPING
IN
A
DS3
SIGNAL
THAT
HAS
A
BIT
RATE
OF
44.736M
BPS
+ 1
PPM
,
INTO
AN
STS-1
SIGNAL
.................................................................................. 63
9.2.2.3 T
HE
44.736M
BPS
- 1
PPM
C
ASE
............................................................................................................................ 64
9.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS ............................................................................... 65
9.3.1 THE CONCEPT OF AN STS-1 SPE POINTER........................................................................................................... 65
F
IGURE
40. A
N
I
LLUSTRATION
OF
THE
STS-1 SPE
TRAFFIC
THAT
WILL
BE
GENERATED
BY
THE
S
OURCE
PTE,
WHEN
MAPPING
A
DS3
SIGNAL
THAT
HAS
A
BIT
RATE
OF
44.736M
BPS
- 1
PPM
,
INTO
AN
STS-1
SIGNAL
................................................................................... 65
F
IGURE
41. A
N
I
LLUSTRATION
OF
AN
STS-1 SPE
STRADDLING
ACROSS
TWO
CONSECUTIVE
STS-1
FRAMES
........................................... 66
9.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK.................................................................................. 67
F
IGURE
42. T
HE
B
IT
-
FORMAT
OF
THE
16-B
IT
W
ORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
10
BITS
,
REFLECTING
THE
LOCATION
OF
THE
J1
BYTE
,
DESIGNATED
.................................................................................................................................................... 67
F
IGURE
43. T
HE
R
ELATIONSHIP
BETWEEN
THE
C
ONTENTS
OF
THE
"P
OINTER
B
ITS
" (
E
.
G
.,
THE
10-
BIT
EXPRESSION
WITHIN
THE
H1
AND
H2
BYTES
)
AND
THE
L
OCATION
OF
THE
J1 B
YTE
WITHIN
THE
E
NVELOPE
C
APACITY
OF
AN
STS-1 F
RAME
.................................................. 67
9.3.3 CAUSES OF POINTER ADJUSTMENTS................................................................................................................... 68
F
IGURE
44. A
N
I
LLUSTRATION
OF
AN
STS-1
SIGNAL
BEING
PROCESSED
VIA
A
S
LIP
B
UFFER
.................................................................... 69
F
IGURE
45. A
N
I
LLUSTRATION
OF
THE
B
IT
F
ORMAT
WITHIN
THE
16-
BIT
WORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
"I"
BITS
DES
-
IGNATED
............................................................................................................................................................................... 70
F
IGURE
46. A
N
I
LLUSTRATION
OF
THE
B
IT
-F
ORMAT
WITHIN
THE
16-
BIT
WORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
"D"
BITS
DES
-
IGNATED
............................................................................................................................................................................... 71
9.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS ............................................................................... 72
9.4 CLOCK GAPPING JITTER ............................................................................................................................. 72
F
IGURE
47. I
LLUSTRATION
OF
THE
T
YPICAL
A
PPLICATIONS
FOR
THE
LIU
IN
A
SONET D
E
-S
YNC
A
PPLICATION
........................................ 72
9.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE)
FOR DS3 APPLICATIONS ............................................................................................................................. 73
T
ABLE
22: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
R
EQUIREMENT
PER
T
ELCORDIA
GR-253-CORE,
FOR
DS3
APPLICATIONS
........ 73
9.5.1 DS3 DE-MAPPING JITTER......................................................................................................................................... 74
9.5.2 SINGLE POINTER ADJUSTMENT............................................................................................................................. 74
9.5.3 POINTER BURST........................................................................................................................................................ 74
F
IGURE
48. I
LLUSTRATION
OF
S
INGLE
P
OINTER
A
DJUSTMENT
S
CENARIO
................................................................................................ 74
9.5.4 PHASE TRANSIENTS................................................................................................................................................. 75
F
IGURE
49. I
LLUSTRATION
OF
B
URST
OF
P
OINTER
A
DJUSTMENT
S
CENARIO
........................................................................................... 75
F
IGURE
50. I
LLUSTRATION
OF
"P
HASE
-T
RANSIENT
" P
OINTER
A
DJUSTMENT
S
CENARIO
............................................................................ 75
9.5.5 87-3 PATTERN............................................................................................................................................................ 76
9.5.6 87-3 ADD..................................................................................................................................................................... 76
F
IGURE
51. A
N
I
LLUSTRATION
OF
THE
87-3 C
ONTINUOUS
P
OINTER
A
DJUSTMENT
P
ATTERN
.................................................................... 76
9.5.7 87-3 CANCEL.............................................................................................................................................................. 77
F
IGURE
52. I
LLUSTRATION
OF
THE
87-3 A
DD
P
OINTER
A
DJUSTMENT
P
ATTERN
....................................................................................... 77
F
IGURE
53. I
LLUSTRATION
OF
87-3 C
ANCEL
P
OINTER
A
DJUSTMENT
S
CENARIO
...................................................................................... 77
9.5.8 CONTINUOUS PATTERN........................................................................................................................................... 78
9.5.9 CONTINUOUS ADD................................................................................................................................................... 78
F
IGURE
54. I
LLUSTRATION
OF
C
ONTINUOUS
P
ERIODIC
P
OINTER
A
DJUSTMENT
S
CENARIO
...................................................................... 78
9.5.10 CONTINUOUS CANCEL........................................................................................................................................... 79
F
IGURE
55. I
LLUSTRATION
OF
C
ONTINUOUS
-A
DD
P
OINTER
A
DJUSTMENT
S
CENARIO
............................................................................... 79
F
IGURE
56. I
LLUSTRATION
OF
C
ONTINUOUS
-C
ANCEL
P
OINTER
A
DJUSTMENT
S
CENARIO
......................................................................... 79
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. .................................. 80
9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM
APPLICATION ................................................................................................................................................ 80
9.7.1 INTRINSIC JITTER TEST RESULTS.......................................................................................................................... 80
T
ABLE
23: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
T
EST
R
ESULTS
"
FOR
SONET/DS3 A
PPLICATIONS
........................................... 80
9.7.2 WANDER MEASUREMENT TEST RESULTS............................................................................................................ 81
9.8 DESIGNING WITH THE LIU ........................................................................................................................... 81
9.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRIN-
SIC JITTER AND WANDER REQUIREMENTS............................................................................................................. 81
F
IGURE
57. I
LLUSTRATION
OF
THE
LIU
BEING
CONNECTED
TO
A
M
APPER
IC
FOR
SONET D
E
-S
YNC
A
PPLICATIONS
................................ 81
C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06.....................................................................82
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0E ............................................................82
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
16.............................................................82
C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06.....................................................................83
相關(guān)PDF資料
PDF描述
XRT75L04 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L04IV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L06DIB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75L04DIV-F 功能描述:外圍驅(qū)動器與原件 - PCI 4-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75L04DIVTR 功能描述:時鐘合成器/抖動清除器 4 CHNL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L04DIVTR-F 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L04ES 功能描述:時鐘合成器/抖動清除器 4CH T3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L04IV 功能描述:外圍驅(qū)動器與原件 - PCI 4CH E3/DS3/STS1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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