參數(shù)資料
型號: XRT75R03IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封裝: 14 X 20 MM, LQFP-128
文件頁數(shù): 4/92頁
文件大?。?/td> 492K
代理商: XRT75R03IV
XRT75R03
REV. 1.0.7
xr
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
I
GENERAL DESCRIPTION.................................................................................................1
FEATURES.........................................................................................................................1
A
PPLICATIONS
................................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75R03.............................................................................................................................. 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
........................................................................................................2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
..........................................................................................................2
F
IGURE
2. P
IN
O
UT
OF
THE
XRT75R03........................................................................................................................................... 3
ORDERING INFORMATION.....................................................................................................................3
PIN DESCRIPTIONS (BY FUNCTION) ..............................................................................4
S
YSTEM
-S
IDE
T
RANSMIT
I
NPUT
AND
T
RANSMIT
C
ONTROL
P
INS
.......................................................................4
T
RANSMIT
L
INE
S
IDE
P
INS
..............................................................................................................................8
S
YSTEM
-S
IDE
R
ECEIVE
O
UTPUT
AND
R
ECEIVE
C
ONTROL
P
INS
......................................................................10
R
ECEIVE
L
INE
S
IDE
P
INS
..............................................................................................................................17
G
ENERAL
C
ONTROL
P
INS
.............................................................................................................................18
C
ONTROL
AND
A
LARM
I
NTERFACE
.................................................................................................................20
J
ITTER
A
TTENUATOR
INTERFACE
...................................................................................................................20
P
OWER
S
UPPLY
AND
G
ROUND
P
INS
.............................................................................................................22
XRT75R03 P
IN
L
ISTING
IN
N
UMERICAL
O
RDER
............................................................................................24
1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) ........................................29
1.1 NETWORK ARCHITECTURE ......................................................................................................................... 29
F
IGURE
3. N
ETWORK
R
EDUNDANCY
A
RCHITECTURE
...................................................................................................................... 29
1.2 POWER FAILURE PROTECTION .................................................................................................................. 29
1.3 SOFTWARE VS HARDWARE AUTOMATIC PROTECTION SWITCHING ................................................... 29
2.0 ELECTRICAL CHARACTERISTICS ....................................................................................................30
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
......................................................................................................................................... 30
T
ABLE
2: DC E
LECTRICAL
C
HARACTERISTICS
:................................................................................................................................ 30
3.0 TIMING CHARACTERISTICS ..............................................................................................................31
F
IGURE
4. T
YPICAL
INTERFACE
BETWEEN
TERMINAL
EQUIPMENT
AND
THE
XRT75R03 (
DUAL
-
RAIL
DATA
).......................................... 31
F
IGURE
5. T
RANSMITTER
T
ERMINAL
I
NPUT
T
IMING
.......................................................................................................................... 31
F
IGURE
6. R
ECEIVER
D
ATA
OUTPUT
AND
CODE
VIOLATION
TIMING
................................................................................................... 32
F
IGURE
7. T
RANSMIT
P
ULSE
A
MPLITUDE
TEST
CIRCUIT
FOR
E3, DS3
AND
STS-1 R
ATES
................................................................. 32
4.0 LINE SIDE CHARACTERISTICS: ........................................................................................................33
4.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 33
F
IGURE
8. P
ULSE
M
ASK
FOR
E3 (34.368
MBITS
/
S
)
INTERFACE
AS
PER
ITU
-
T
G.703......................................................................... 33
T
ABLE
3: E3 T
RANSMITTER
LINE
SIDE
OUTPUT
AND
RECEIVER
LINE
SIDE
INPUT
SPECIFICATIONS
........................................................ 34
F
IGURE
9. B
ELLCORE
GR-253 CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE
FOR
SONET STS-1 A
PPLICATIONS
............................. 35
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
..................................................................................................................................... 35
T
ABLE
5: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) .............................. 36
F
IGURE
10. T
RANSMIT
O
UPUT
P
ULSE
T
EMPLATE
FOR
DS3
AS
PER
B
ELLCORE
GR-499................................................................... 37
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................ 37
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) ................................. 38
F
IGURE
11. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
S
TRUCTURE
...................................................................................................... 38
F
IGURE
12. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................ 39
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V± 5%
AND
LOAD
= 10
P
F).................................. 39
FUNCTIONAL DESCRIPTION:........................................................................................40
5.0 THE TRANSMITTER SECTION: ..........................................................................................................40
F
IGURE
13. S
INGLE
-R
AIL
OR
NRZ D
ATA
F
ORMAT
(E
NCODER
AND
D
ECODER
ARE
E
NABLED
)............................................................ 40
F
IGURE
14. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER
AND
DECODER
ARE
DISABLED
)............................................................................. 40
5.1 TRANSMIT CLOCK: ....................................................................................................................................... 41
5.2 B3ZS/HDB3 ENCODER: ................................................................................................................................. 41
5.2.1 B3ZS ENCODING: ...................................................................................................................................................... 41
F
IGURE
15. B3ZS E
NCODING
F
ORMAT
........................................................................................................................................... 41
5.2.2 HDB3 ENCODING:...................................................................................................................................................... 41
F
IGURE
16. HDB3 E
NCODING
F
ORMAT
.......................................................................................................................................... 41
5.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 42
5.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT:................................................................................. 42
5.3.2 INTERFACING TO THE LINE:.................................................................................................................................... 42
5.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 43
F
IGURE
17. T
RANSMIT
D
RIVER
M
ONITOR
SET
-
UP
............................................................................................................................ 43
5.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 43
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