參數(shù)資料
型號: XRT75R12IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PBGA420
封裝: 35 X 35 MM, TBGA-420
文件頁數(shù): 13/89頁
文件大小: 457K
代理商: XRT75R12IB
PRELIMINARY
XRT75R12
REV. P1.0.2
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
10
GENERAL CONTROL PINS
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
P3
TEST
****
Factory Test Mode Input Pin
This pin must be connected to GND for normal operation.
N
OTE
:
This input pin is internally pulled "Low".
AE25
TRST
I
Test Reset
Test Boundary Scan
AB23
TMS
I
Test Mose Select
Test Boundary Scan
AB5
TCK
I
Test Clock
Test Boundary Scan
AB4
TDI
I
Test Data Input
Test Boundary Scan
AE2
TDO
O
Test Data Output
Test Boundary Scan
MICROPROCESSOR PARALLEL INTERFACE -
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
J26
Pmode
I
This pin controls the Microprocessor Parallel Interface mode.
"High" sets a Synchronous clocked interface mode with a clock from the
Host.
"Low" sets an Asynchronous mode where a clock internal to the
XRT75R12 will time the operations.
High speed clock supplied by the Host to provide timing in the
Synchronous Interface mode. This signal must be a square-wave.
Chip select input (active low)
Initiates a read or write operation. When "High", no parallel
communication is active between the LIU and the Host.
Write input (active low)
Enables the Host to write data D[7:0] into the LIU register space at
address Addr[7:0].
Read input (active low)
Commands the LIU to transfer the contents of a register specified by
Addr[7:0] to the Host.
Ready line output (active low)
Provides a handshake between the LIU and the Host that communicates
when an operation has been completed.
N
OTE
:
This pin must be pulled "High" with a 3k
± 1% resistor.
P24
PCLK
I
N24
CS
I
N22
WR
I
N23
RD
I
N25
RDY
O
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