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參數(shù)資料
| 型號： | XRT75R12IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA420 |
| 封裝： | 35 X 35 MM, TBGA-420 |
| 文件頁數(shù)： | 3/89頁 |
| 文件大?。?/td> | 457K |
| 代理商： | XRT75R12IB |
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XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
PRELIMINARY
TABLE OF CONTENTS
REV. P1.0.2
I
GENERAL DESCRIPTION.............................................................................................................. 1
A
PPLICATIONS
............................................................................................................................................................... 1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 75R12 .................................................................................................................................... 1
ORDERING INFORMATION ....................................................................................................................1
F
EATURES
..................................................................................................................................................................... 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
....................................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
......................................................................................................................... 2
PIN DESCRIPTIONS (BY FUNCTION).......................................................................................... 3
S
YSTEM
-S
IDE
T
RANSMIT
I
NPUT
AND
T
RANSMIT
C
ONTROL
P
INS
....................................................................................... 3
S
YSTEM
-S
IDE
R
ECEIVE
O
UTPUT
AND
R
ECEIVE
C
ONTROL
P
INS
....................................................................................... 6
R
ECEIVE
L
INE
S
IDE
P
INS
............................................................................................................................................... 8
C
LOCK
I
NTERFACE
......................................................................................................................................................... 9
G
ENERAL
C
ONTROL
P
INS
............................................................................................................................................ 10
P
OWER
S
UPPLY
P
INS
.................................................................................................................................................. 12
G
ROUND
P
INS
............................................................................................................................................................. 13
FUNCTIONAL DESCRIPTION...................................................................................................... 18
1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) .......................................18
1.1 NETWORK ARCHITECTURE ......................................................................................................................... 18
F
IGURE
2. N
ETWORK
R
EDUNDANCY
A
RCHITECTURE
............................................................................................................................. 18
2.0 CLOCK SYNTHESIZER .......................................................................................................................19
2.1 CLOCK DISTRIBUTION ................................................................................................................................. 19
F
IGURE
4. C
LOCK
D
ISTRIBUTION
C
ONGIFURED
IN
E3 M
ODE
W
ITHOUT
U
SING
SFM................................................................................ 19
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
I
NPUT
C
LOCK
C
IRCUITRY
D
RIVING
THE
M
ICROPROCESSOR
............................................ 19
3.0 THE RECEIVER SECTION ..................................................................................................................20
F
IGURE
5. R
ECEIVE
P
ATH
B
LOCK
D
IAGRAM
.......................................................................................................................................... 20
3.1 RECEIVE LINE INTERFACE .......................................................................................................................... 20
F
IGURE
6. R
ECEIVE
L
INE
I
NTERFACE
C
ONNECTION
................................................................................................................................. 20
3.2 ADAPTIVE GAIN CONTROL (AGC) .............................................................................................................. 21
3.3 RECEIVE EQUALIZER ................................................................................................................................... 21
F
IGURE
7. ACG/E
QUALIZER
B
LCOK
D
IAGRAM
....................................................................................................................................... 21
3.3.1 RECOMMENDATIONS FOR EQUALIZER SETTINGS.............................................................................................. 21
3.4 CLOCK AND DATA RECOVERY ................................................................................................................... 21
3.4.1 DATA/CLOCK RECOVERY MODE............................................................................................................................ 21
3.4.2 TRAINING MODE........................................................................................................................................................ 21
3.5 LOS (LOSS OF SIGNAL) DETECTOR ........................................................................................................... 22
3.5.1 DS3/STS-1 LOS CONDITION..................................................................................................................................... 22
3.5.2 DISABLING ALOS/DLOS DETECTION ..................................................................................................................... 22
T
ABLE
2: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) .......................................................................................................................................................... 22
3.5.3 E3 LOS CONDITION:.................................................................................................................................................. 23
F
IGURE
8. L
OSS
O
F
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775 .................................................................................................. 23
F
IGURE
9. L
OSS
OF
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775................................................................................................... 23
3.5.4 INTERFERENCE TOLERANCE.................................................................................................................................. 24
F
IGURE
10. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
DS3/STS-1...................................................................................................... 24
F
IGURE
11. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
E3.................................................................................................................... 24
T
ABLE
3: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
................................................................................................................................. 25
3.5.5 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 26
3.6 B3ZS/HDB3 DECODER .................................................................................................................................. 26
F
IGURE
12. R
ECEIVER
D
ATA
OUTPUT
AND
CODE
VIOLATION
TIMING
........................................................................................................ 26
4.0 THE TRANSMITTER SECTION ...........................................................................................................27
F
IGURE
13. T
RANSMIT
P
ATH
B
LOCK
D
IAGRAM
...................................................................................................................................... 27
4.1 TRANSMIT DIGITAL INPUT INTERFACE ..................................................................................................... 27
F
IGURE
14. T
YPICAL
INTERFACE
BETWEEN
TERMINAL
EQUIPMENT
AND
THE
XRT75R12 (
DUAL
-
RAIL
DATA
) .............................................. 27
F
IGURE
15. T
RANSMITTER
T
ERMINAL
I
NPUT
T
IMING
............................................................................................................................... 28
F
IGURE
16. S
INGLE
-R
AIL
OR
NRZ D
ATA
F
ORMAT
(E
NCODER
AND
D
ECODER
ARE
E
NABLED
).................................................................. 28
4.2 TRANSMIT CLOCK ........................................................................................................................................ 29
4.3 B3ZS/HDB3 ENCODER .................................................................................................................................. 29
4.3.1 B3ZS ENCODING ....................................................................................................................................................... 29
4.3.2 HDB3 ENCODING....................................................................................................................................................... 29
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