參數(shù)資料
型號: XRT75VL00
廠商: Exar Corporation
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述: E3/DS3/STS-1線路接口單元與抖動衰減器
文件頁數(shù): 38/50頁
文件大?。?/td> 268K
代理商: XRT75VL00
XRT75VL00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.3
36
clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL is set to “1”
in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
N
OTE
:
It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter.
Table 13 specifies the jitter transfer mask requirements for various data rates:
The jitter attenuator within the XRT75VL00 meets the latest jitter attenuation specifications and/or jitter transfer
characteristics as shown in the Figure 24.
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
R
ATE
(
KBITS
)
M
ASK
F1
(H
Z
)
F2
(H
Z
)
F3
(H
Z
)
F4
(
K
H
Z
)
A1(dB)
A2(dB)
34368
G.823
ETSI-TBR-24
100
300
3
K
800
K
0.5
-19.5
44736
GR-499, Cat I
GR-499, Cat II
GR-253 CORE
10
10
10
10k
56.6k
40
-
-
-
15k
300k
15k
0.1
0.1
0.1
-
-
-
51840
GR-253 CORE
10
40k
-
400k
0.1
-
F
IGURE
24. J
ITTER
T
RANSFER
R
EQUIREMENTS
AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
F1
A1
F2
J
JITTER FREQUENCY (kHz)
A2
F3
F4
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