參數(shù)資料
型號: XRT75VL00DIVTR
廠商: Exar Corporation
文件頁數(shù): 44/92頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 1CH 52TQFP
標準包裝: 1,000
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應(yīng)商設(shè)備封裝: 52-TQFP(10x10)
包裝: 帶卷 (TR)
XRT75VL00D
44
REV. 1.0.4
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75VL00D can be configured in Analog Loopback either in Hardware mode via the LLB and RLB pins or in
Host mode via LLB and RLB bits in the channel control registers.
NOTES:
1.
In the Analog loopback mode, data is also output via TTIP and TRING pins.
2.
Signals on the RTIP and RRING pins are ignored during analog loopback.
8.2.2
DIGITAL LOOPBACK:
The Digital Loopback function is available either in Hardware mode or Host mode. When the Digital Loopback
is selected, the transmit clock (TxClk) and transmit data inputs (TPDATA & TNDATA) are looped back and
output onto the RxClk, RPOS and RNEG pins as shown in Figure 27. The data presented on TxClk, TPDATA
and TNDATA are not output on the TTIP and TRING pins.This provides the capability to configure the
protection card (in redundancy applications) in Digital Loopback mode without affecting the traffic on the
primary card.
NOTE: Signals on the RTIP and RRING pins are ignored during digital loopback.
FIGURE 26. ANALOG LOOPBACK
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS1
ENCODER
HDB3/B3ZS1
DECODER
J
IT
T
E
R
2
A
T
E
N
U
A
T
O
R
J
IT
T
E
R
2
A
T
E
N
U
A
T
O
R
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1 if enabled
2 if enabled and selected in either Receive or Transmit path
Tx
Rx
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