參數(shù)資料
型號: XRT75VL00DIVTR
廠商: Exar Corporation
文件頁數(shù): 86/92頁
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 1CH 52TQFP
標準包裝: 1,000
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應商設備封裝: 52-TQFP(10x10)
包裝: 帶卷 (TR)
XRT75VL00D
82
REV. 1.0.4
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
HOW MAJOR PATTERN B IS SYNTHESIZED
MAJOR PATTERN B is created (by the Mapper IC) by:
Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times.
Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times.
pon completion of the 35th transmission of MINOR PATTERN P2, MINOR PATTERN P3 is transmitted once.
Figure 62 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN B.
Hence, MAJOR PATTERN B consists of "(63 x 7) + (35 x 5)" + 6 = 622 clock pulses.
These 622 clock pulses were delivered over a period of "(63 x 8) + (35 x 6) + 6 = 720 STS-1 (or 51.84MHz)
clock periods.
PUTTING THE PATTERNS TOGETHER
Finally, the DS3 to OC-N Mapper IC clock output is reproduced by doing the following.
MAJOR PATTERN A is transmitted two times (repeatedly).
After the second transmission of MAJOR PATTERN A, MAJOR PATTERN B is transmitted once.
Then the whole process repeats.
Throughout the remainder of this document, we will refer to this particular pattern as the "SUPER PATTERN".
Figure 63 presents an illustration of this "SUPER PATTERN" which is output via the Mapper IC.
FIGURE 61. ILLUSTRATION OF MINOR PATTERN P3
FIGURE 62. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B
1
2
3
4
5
6
PATTERN P1
PATTERN P2
Repeats 63 Times
Repeats 35 Times
PATTERN P3
Transmitted 1 Time
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