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| 型號： | XRT75VL00DIVTR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 60/92頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| 標準包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應商設備封裝： | 52-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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XRT75VL00D
58
REV. 1.0.4
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
As a consequence, no "Mapping/De-Mapping" Jitter or Wander is induced in the "Ideal Case".
9.2.2.2
The 44.736Mbps + 1ppm Case
The "above example" was a very ideal case. In reality, there are going to be frequency offsets in both the DS3
and STS-1 signals. For instance Bellcore GR-499-CORE mandates that a DS3 signal have a bit rate of
44.736Mbps ± 20ppm. Hence, the bit-rate of a "Bellcore" compliant DS3 signal can vary from the exact correct
frequency for DS3 by as much of 20ppm in either direction. Similarly, many SONET applications mandate that
SONET equipment use at least a "Stratum 3" level clock as its timing source. This requirement mandates that
an STS-1 signal must have a bit rate that is in the range of 51.84 ± 4.6ppm. To make matters worse, there are
also provisions for SONET equipment to use (what is referred to as) a "SONET Minimum Clock" (SMC) as its
timing source. In this case, an STS-1 signal can have a bit-rate in the range of 51.84Mbps ± 20ppm.
In order to convey the impact that frequency offsets (in either the DS3 or STS-1 signal) will impose on the bit-
stuffing behavior, and the resulting bit-rate, intrinsic jitter and wander within the DS3 signal that is being
transported across the SONET network; let us assume that a DS3 signal, with a bit-rate of 44.736Mbps +
1ppm is being mapped into an STS-1 signal with a bit-rate of 51.84Mbps + 0ppm. In this case, the following
things will occur.
In general, most of the STS-1 SPE's will each transport 5592 DS3 data bits.
However, within a "one-second" period, a DS3 signal that has a bit-rate of 44.736Mbps + 1 ppm will deliver
approximately 44.7 additional bits (over and above that of a DS3 signal with a bit-rate of 44.736Mbps + 0
ppm). This means that this particular signal will need to "negative-stuff" or map in an additional DS3 data bit
every (1/44.736 =) 22.35ms. In other words, this additional DS3 data bit will need to be mapped into about
one in every (22.35ms 8000 =) 178.8 STS-1 SPEs in order to avoid dropping any DS3 data-bits.
What does this mean at the "Source" PTE?
All of this means that as the "Source" PTE maps this DS3 signal, with a data rate of 44.736Mbps + 1ppm into
an STS-1 signal, most of the resulting "outbound" STS-1 SPEs will transport 5592 DS3 data bits (e.g., 3 Stuff
Opportunity bits will be carrying DS3 data bits, the remaining 6 Stuff Opportunity bits are "stuff" bits, as in the
"Ideal" case). However, in approximately one out of 178.8 "outbound" STS-1 SPEs, there will be a need to
insert an additional DS3 data bit within this STS-1 SPE. Whenever this occurs, then (for these particular STS-
1 SPEs) the SPE will be carrying 5593 DS3 data bits (e.g., 4 Stuff Opportunity bits will be carrying DS3 data
bits, the remaining 5 Stuff Opportunity bits are "stuff" bits).
Figure 39 presents an illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, during
this condition.
FIGURE 39. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE,
WHEN MAPPING IN A
DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL
Source
PTE
Source
PTE
44.736Mbps + 1ppm
5592
DS3 Data
Bits
5592
DS3 Data
Bits
5592
DS3 Data
Bits
5592
DS3 Data
Bits
SPE # N
SPE # N+1
5592
DS3 Data
Bits
5592
DS3 Data
Bits
SPE # N+177
5593
DS3 Data
Bits
5593
DS3 Data
Bits
5592
DS3 Data
Bits
5592
DS3 Data
Bits
SPE # N+178
SPE # N+179
Extra DS3 Data
Bit Stuffed Here
STS-1 SPE Data Stream
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75VL00DIVTR-F | 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75VL00ES | 功能描述:時鐘合成器/抖動清除器 1CHT3/E3/STS1LIU+A 3.3V VOLTAGE DRIVE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75VL00IV | 功能描述:外圍驅(qū)動器與原件 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75VL00IV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75VL00IVTR | 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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