參數(shù)資料
型號： XRT79L72
廠商： Exar Corporation
英文描述： 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
中文描述： 2 -通道DS3/E3自動柜員機用戶到網(wǎng)絡接口/ Combo IC對購買力平價
文件頁數(shù)： 13/72頁
文件大?。?/td> 441K
代理商： XRT79L72
xr
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PRELIMINARY
XRT79L72
REV. P1.0.2
10
G2
D23
TxOHFrame
_0
/
TxHDLCClk
_0
TxOHFrame
_1
/
TxHDLCClk
_1
O
O
Transmit Overhead Framing Pulse/Transmit HDLC Controller Clock Output
pin:
The function of these output pins depend upon whether or not the XRT79L72
has been configured to operate in the High-Speed HDLC Controller Mode.
Non-High-Speed HDLC Controller Mode - TxOHFrame:
These output pins pulse high for one TxOHClk period coincident with the instant
the Transmit Overhead Data Input Interface would be accepting the first over-
head bit within an outbound DS3 or E3 frame.
High Speed HDLC Controller Mode - TxHDLCClk:
This output pin functions as the "demand" clock output signal for the "Transmit
HDLC Controller" byte-wide input interface. This clock signal is ultimately
derived from either the TxInClk clock signal (for Local-Timing Applications) or the
RxOutClk clock signal (for Loop-Timing Applications). Hence, the frequency of
this clock signal is nominally one-eight of that of the TxInClk or the RxOutClk sig-
nals.
The Transmit HDLC Controller block will sample the contents of the Transmit
HDLC Controller byte-wide input interface, upon the rising edge of these clock
output signals. Therefore, the local terminal equipment should be designed to
output data onto the TxHDLCDatn_[7:0] bus upon the falling edge of these clock
output signals.
R2
M24
TxOHEnable
_0
/
TxHDLCDat
0
_7
TxOHEnable
_1
/
TxHDLCDat
0
_2
I/O
I/O
Transmit Overhead Enable Output indicator/Transmit HDLC Controller Data
Bit 7 Input:
The function of these input pins depend upon whether or not the XRT79L72 is
configured to operate in the High Speed HDLC Controller Mode.
Non-High Speed HDLC Controller Mode - TxOHEnable:
The XRT79L72 will assert these output pins, for one TxInClk period, just prior to
the instant that the Transmit Overhead Data Input Interface will be sampling and
processing an overhead bit.
If the local terminal equipment intends to insert its own value for an overhead bit,
into the outbound DS3 or E3 data stream, then it is expected to sample the state
of these signals, upon the falling edge of TxInClk. Upon sampling the TxOHEn-
able signal "High", the local terminal equipment should;
(1) place the desired value of the overhead bit onto the TxOH input pin and
(2) assert the TxOHIns input pin.
The Transmit Overhead Data Input Interface block will sample and latch the data
on the TxOH signal, upon the rising edge of the very next TxInClk input signal.
High-Speed HDLC Controller Mode - TxHDLCDat_7:
If the XRT79L72 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 7 (the MSB) within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT79L72IB 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73IB 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT79L72IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73 制造商:EXAR 制造商全稱:EXAR 功能描述:3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73IB 制造商:EXAR 制造商全稱:EXAR 功能描述:3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74IB 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
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