參數(shù)資料
型號(hào)： XRT79L72
廠商： Exar Corporation
英文描述： 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
中文描述： 2 -通道DS3/E3自動(dòng)柜員機(jī)用戶到網(wǎng)絡(luò)接口/ Combo IC對(duì)購買力平價(jià)
文件頁數(shù)： 5/72頁
文件大?。?/td> 441K
代理商： XRT79L72
xr
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PRELIMINARY
XRT79L72
REV. P1.0.2
II
TRANSMIT PAYLOAD DATA INPUT INTERFACE ........................................................55
TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS.....................................55
T
ABLE
9: T
IMING
INFORMATION
FO
RTHE
T
RNASMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
BLOCK
.......................................................... 55
F
IGURE
11. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
WHEN
THE
XRT79L72
IS
OPERATING
IN
BOTH
THE
DS3
AND
L
OOP
-T
IMING
M
ODES
.............................................................................................................................................. 56
F
IGURE
12. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
WHEN
THE
XRT79L72
IS
OPERATING
IN
BOTH
THE
DS3
AND
L
OCAL
-T
IMING
M
ODES
............................................................................................................................................. 57
F
IGURE
13. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
WHEN
THE
XRT79L72
IS
OPERATING
IN
BOTH
THE
DS3/
N
IBBLE
-P
ARALLEL
AND
L
OOP
-T
IMING
M
ODES
.................................................................................................................. 57
F
IGURE
14. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
WHEN
THE
XRT79L72
IS
OPERATING
IN
BOTH
THE
DS3/
N
IBBLE
-P
ARALLEL
AND
L
OCAL
-T
IMING
M
ODES
................................................................................................................. 58
TRANSMIT OVERHEAD DATA INPUT INTERFACE......................................................59
TRANSMIT OVERHEAD DATA INPUT INTERFACE - TIMING REQUIREMENTS..................................59
T
ABLE
10: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
O
VERHEAD
D
ATA
I
NPUT
I
NTERFACE
B
LOCK
..................................................... 59
F
IGURE
15. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
O
VERHEAD
D
ATA
I
NPUT
I
NTERFACE
(M
ETHOD
1 A
CCESS
).................................... 61
F
IGURE
16. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
O
VERHEAD
D
ATA
I
NPUT
I
NTERFACE
(M
ETHOD
2 A
CCESS
).................................... 61
RECEIVE PAYLOAD DATA OUTPUT INTERFACE.......................................................62
RECEIVE PAYLOAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ...................................62
T
ABLE
11: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
P
AYLOAD
D
ATA
O
UTPUT
I
NTERFACE
B
LOCK
...................................................... 62
F
IGURE
17. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
P
AYLOAD
D
ATA
O
UTPUT
I
NTERFACE
(S
ERIAL
M
ODE
).............................................. 62
F
IGURE
18. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
P
AYLOAD
D
ATA
O
UTPUT
I
NTERFACE
(N
IBBLE
-P
ARALLEL
M
ODE
) ............................. 63
RECEIVE OVERHEAD DATA OUTPUT INTERFACE ....................................................64
RECEIVE OVERHEAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS................................64
AC E
LECTRICAL
C
HARACTERISTICS
(C
ONT
.).................................................................................................64
F
IGURE
19. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
O
VERHEAD
D
ATA
O
UTPUT
I
NTERFACE
(M
ETHOD
1 - U
SING
R
X
OHC
LK
).................. 65
F
IGURE
20. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
O
VERHEAD
D
ATA
O
UTPUT
I
NTERFACE
(M
ETHOD
2 - U
SING
R
X
OHE
NABLE
)............ 65
RECEIVE UTOPIA INTERFACE......................................................................................66
RECEIVE UTOPIA INTERFACE...............................................................................................................66
F
IGURE
21. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
UTOPIA I
NTERFACE
B
LOCK
.................................................................................. 66
T
ABLE
12: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
UTOPIA I
NTERFACE
B
LOCK
............................................................................. 66
ORDERING INFORMATION............................................................................................68
PACKAGE DIMENSIONS................................................................................................68
R
EVISION
H
ISTORY
......................................................................................................................................69
相關(guān)PDF資料
PDF描述
XRT79L72IB 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73IB 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74IB 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT79L72IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73 制造商:EXAR 制造商全稱:EXAR 功能描述:3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73IB 制造商:EXAR 制造商全稱:EXAR 功能描述:3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L74IB 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
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