Rev. 1.01 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 18 17 XRT8001 SDO SYNC FIN GND CLK1 VCC MSB GND VCC LOCKDET VCC CLK2 GND VCC SDI CS " />
參數(shù)資料
型號(hào): XRT8001IDTR-F
廠商: Exar Corporation
文件頁數(shù): 23/48頁
文件大?。?/td> 0K
描述: IC WAN CLOCK E1/E1 DUAL 18SOIC
產(chǎn)品變化通告: Packaging Change 15/Jul/2010
標(biāo)準(zhǔn)包裝: 1,000
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: 以太網(wǎng)(WAN),T1/E1
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 16.384kHz
電源電壓: 3.3 V ~ 5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 18-SOIC
包裝: 帶卷 (TR)
XRT8001
3
Rev. 1.01
1
2
3
4
5
6
7
9
8
10
11
12
13
14
15
16
18
17
XRT8001
SDO
SYNC
FIN
GND
CLK1
VCC
MSB
GND
VCC
LOCKDET
VCC
CLK2
GND
VCC
SDI
CS
SCLK
Figure 3. XRT8001 PIN OUT
PIN DESCRIPTION
Pin #
Name
Type
Description
1
SDO
O
Serial Data Output from the Microprocessor Serial Interface
This pin will serially output the contents of the specified Command
Register, during “Read” Operations. The data, on this pin, will be
updated on the falling edge of the SCLK input signal. This pin will be tri-
stated upon completion of data transfer.
2
SYNC
O
Sync Output - The XRT8001 will typically output an 8kHz clock signal
via this output pin.
However, when the XRT8001 is operating in the “High Speed - Reverse”
Mode, then this device will simply output a 64kHz clock signal.
3
FIN
I
Reference Clock Input - The Reference Timing signal (from which the
CLK1 and CLK2 output signals are derived) is to be input via this pin.
4
GND
-
Digital Ground
5
GND
-
Digital Ground
6
CLK1
O
Clock Output 1 - The XRT8001 will drive the desired “synthesized”
signal via this output pin. This output signal will have a 50+5% duty
cycle.
Note: This output pin is tri-stated unless the “CLK1EN” bit-field (within
Command Register CR4) has been set to “1”.
7
V
CC
-
Digital Power Supply
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