Rev. 1.01 9.0 Generating a 1.544MHz clock signal via the “CLK1/CLK2” outputs from either a 1.544MHz, or a 2.048MHz clock signal When" />
參數(shù)資料
型號(hào): XRT8001IDTR-F
廠商: Exar Corporation
文件頁數(shù): 33/48頁
文件大小: 0K
描述: IC WAN CLOCK E1/E1 DUAL 18SOIC
產(chǎn)品變化通告: Packaging Change 15/Jul/2010
標(biāo)準(zhǔn)包裝: 1,000
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: 以太網(wǎng)(WAN),T1/E1
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 16.384kHz
電源電壓: 3.3 V ~ 5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 18-SOIC
包裝: 帶卷 (TR)
XRT8001
39
Rev. 1.01
9.0 Generating a 1.544MHz clock signal via the
“CLK1/CLK2” outputs from either a 1.544MHz, or a
2.048MHz clock signal
When approaching this problem, be aware that the
XRT8001 WAN Clock can be configured to accept a
2.048MHz clock signal via the “FIN” input pin and
generate a 1.544MHz clock signal. However, the
XRT8001 WAN Clock cannot be configured to accept
a 1.544MHz clock signal, and generate a 1.544MHz
clock signal.
Also, note the XRT8001 WAN Clock can be configured
to accept a 2.048MHz clock signal (via the “FIN” input)
and generate a 1.544MHz clock signal if it configured
to operate in the “E1 to T1 Forward/Master” Mode. The
XRT8001 can similarly be configured to accept an
8kHz clock signal (via the same “FIN” input pin) and
generate a 1.544MHz clock signal if it is configured to
operate in the “Reverse/Slave” Mode.
Based upon these two points, the necessary circuitry
(in order to synthesize a 1.544MHz clock signal, from
either a 1.544MHz or a 2.048MHz clock signal) can be
achieved by the approach shown below in a block
diagram.
Divide by
193
Divide by
193
2 : 1 MUX
SE
L
FIN
MSB
CLK1
CLK2
XRT8001 WAN Clock
1.544MHz or 2.048MHz Clock Signal
E1/T1* SELECT
1.544MHz
8kHz
2.048MHz or 8kHz Clock Signal
Divide by
193
Divide by
193
2 : 1 MUX
SEL
FIN
MSB
CLK1
CLK2
XRT8001 WAN Clock
1.544MHz or 2.048MHz Clock Signal
E1/T1* SELECT
1.544MHz
8kHz
2.048MHz or 8kHz Clock Signal
In Figure 23, the 1.544MHz or 2.048MHz input clock
signal is routed to two locations.
One of the inputs of a “2:1 MUX”.
The “CU” input of a “Divide-by-193” Block.
Figure 23 also includes a digital “E1/T1* SELECT”
signal. This signal is connected to both the “SEL” input
of the “2:1 MUX” and the “MSB” input of the XRT8001
WAN Clock. The basic idea behind this schematic is
as follows:
1. If the incoming clock signal (from the T1/E1 LIU for
example) is a 1.544MHz clock signal, then this signal
will be divided by 193. As it passes through the “Divide-
by-193” block a 8kHz clock signal is generated. This
8kHz clock signal will be applied to one of the inputs to
the “2:1 MUX”. (NOTE: A 1.544MHz clock signal is
applied to the other input to the “2:1 MUX”).
In this case, the user must set the “E1/T1* SELECT”
signal to “LOW”, order to select “T1 rates” (1.544MHz).
By doing this, the 8kHz output from the “Divide-by-193”
block is selected and will be applied to the “FIN” input
of the XRT8001; and the XRT8001 will be configured to
operate in the “Slave” Mode.
At this point, the user will need to execute the appro-
priate steps in order to configure the XRT8001 into the
“Reverse-Slave” Mode.
2. If the incoming clock signal (from the T1/E1 LIU) is
a 2.048MHz clock signal, then this signal will also be
divided by 193. As it passes through the “Divide-by-
193” block, it generates a clock signal of a strange (and
undesirable frequency).
This clock signal will be
applied to one of the inputs to the “2:1 MUX” (NOTE:
The 2.048MHz clock will also be applied to the other
input of the “2:1 MUX).
Figure 23: Synthesizing a 1.544MHz clock signal from a 1.544MHz or 2.048MHz clock
相關(guān)PDF資料
PDF描述
VE-JTV-MX-F3 CONVERTER MOD DC/DC 5.8V 75W
VE-JTV-MX-F1 CONVERTER MOD DC/DC 5.8V 75W
VE-JTT-MX-F4 CONVERTER MOD DC/DC 6.5V 75W
VE-JTT-MX-F3 CONVERTER MOD DC/DC 6.5V 75W
VE-JTT-MX-F1 CONVERTER MOD DC/DC 6.5V 75W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT8001IP 制造商:EXAR 制造商全稱:EXAR 功能描述:WAN Clock for T1 and E1 Systems
XRT8001IP-F 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
XRT8010 制造商:EXAR 制造商全稱:EXAR 功能描述:312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
XRT8010ES 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
XRT8010IL 制造商:EXAR 制造商全稱:EXAR 功能描述:312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS