Rev. 1.01 Value of “M” Value to be Written into Command Register CR2 1 0000X 2 0001X 4 001XX 8 X1XX or 1XXX Table 7. Relationship Be" />
參數資料
型號: XRT8001IDTR-F
廠商: Exar Corporation
文件頁數: 24/48頁
文件大?。?/td> 0K
描述: IC WAN CLOCK E1/E1 DUAL 18SOIC
產品變化通告: Packaging Change 15/Jul/2010
標準包裝: 1,000
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: 以太網(WAN),T1/E1
輸入: 時鐘
輸出: 時鐘
電路數: 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 16.384kHz
電源電壓: 3.3 V ~ 5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 18-SOIC
包裝: 帶卷 (TR)
XRT8001
30
Rev. 1.01
Value of “M”
Value to be Written into
Command Register CR2
1
0000X
2
0001X
4
001XX
8
X1XX or 1XXX
Table 7. Relationship Between the Value of
“M” and the Value to Be Written into Command
Register CR2 (in Order to Configure the “CLK1”
Output Frequency)
Note: The expression “X” indicates a “Don’t Care” value for
that particular bit-field.
Command Register, CR2 (Address = 0x02)
D4
D3
D2
D1
D0
SEL14
SEL13
SEL12
SEL11
SEL10
Value from Table 7
Step 5 – Specify the value for “M” (e.g., as in the “M x
2.048MHz” clock signal) which is to be the output on
the “CLK2” output pin.
This is accomplished by reviewing Table 8, and deter-
mining the 5-bit binary value which corresponds with
the desired value of “M”. Afterwards, the user should
write this value into Command Register, CR3.
Value of “M”
Value to be Written into
Command Register CR3
1
0000X
2
0001X
4
001XX
8
X1XXX or 1XXXX
Table 8. Relationship Between the Value of
“M” and the Value to Be Written into Command
Register CR3 (in Order to Configure the “CLK2”
Output Frequency)
Note: The expression “X” indicates a “Don’t Care” value
for that particular bit-field.
Command Register, CR3 (Address = 0x03)
D4
D3
D2
D1
D0
SEL24
SEL23
SEL22
SEL21
SEL20
Value from Table 8
Step 6 – Enable any of the following output signals as
appropriate:
“SYNC”, “CLK1”, “CLK2” and
“LOCKDET”.
This is accomplished by writing a “1” into the corre-
sponding bit-fields, within Command Register CR4, as
illustrated below:
Command Register CR4, (Address = 0x04)
D4
D3
D2
D1
D0
SYNCEN
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
1
0
6.8 The "Forward/Slave" Mode
When the XRT8001 WAN Clock has been configured to
operate in the “Forward/Slave” Mode, then it will accept
an 8kHz clock signal via the “Reference Clock” input at
FIN (pin 3). In response to this clock signal, the
XRT8001 WAN Clock will output either a “L x 56kHz” or
“L x 64kHz” clock signal via the “Clock Output pins”
(CLK1 and CLK2); where L can range in value from 1 to
32.
A simple illustration of the XRT8001 WAN Clock
operating in the "Forward/Slave" Mode” is presented in
Figure 18.
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