參數(shù)資料
型號: XRT83VSH28IB
廠商: Exar Corporation
文件頁數(shù): 37/75頁
文件大?。?/td> 0K
描述: IC LIU SH E1 OCTAL 225BGA
標準包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83VSH28
39
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 2.0.0
5.0
MICROPROCESSOR INTERFACE
The microprocessor interface can be accessed through a standard serial interface (BGA Package Only) or a
standard parallel microprocessor interface. The SER_PAR pin is used to select between the two. By default,
the chip is configured in the Parallel Microprocessor interace. For Serial communication, this pin must be
pulled “High”.
5.1
Serial Microprocessor Interface Block (BGA Package Only)
The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the LIU.
Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers, monitor
the LIU via an interrupt pin, and reset the LIU to its default configuration by pulling reset "Low" for more than
10
S. A simplified block diagram of the Serial Microprocessor is shown in Figure 28.
5.1.1
Serial Timing Information
The serial port requires 24 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor
samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device until all 24
bits of serial data have been sampled. A timing diagram of the Serial Microprocessor is shown in Figure 29.
NOTE: For applications without a free running SCLK, a minimum of 1 SCLK pulse must be applied when CS is “High”,
befrore pulling CS “Low”.
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE
FIGURE 29. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE
Serial
Microprocessor
Interface
CS
SDI
SCLK
SDO
RESET
INT
HW/Host
SER_PAR
R/W
ADDR[0] - ADDR[7]
Don't Care
DATA[0] - DATA[7]
CS
SDI
SCLK
8-Bit Address
8-Bit Data
7-Bit Don't Care
1=Read
0=Write
SDO
DATA[0] - DATA[7]
Readback
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