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參數(shù)資料
型號(hào): XRT83VSH28IB
廠商: Exar Corporation
文件頁(yè)數(shù): 56/75頁(yè)
文件大?。?/td> 0K
描述: IC LIU SH E1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83VSH28
II
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 2.0.0
TABLE 8: RANDOM BIT SEQUENCE POLYNOMIALS ........................................................................................................................... 30
3.6 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 31
3.7 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 31
FIGURE 18. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 31
4.0 E1 APPLICATIONS ..............................................................................................................................32
4.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 32
4.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 32
FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 32
4.1.2 REMOTE LOOPBACK ................................................................................................................................................ 32
FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .................................................................................................... 32
4.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 33
FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 33
4.1.4 DUAL LOOPBACK ..................................................................................................................................................... 33
FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ........................................................................................................ 33
4.2 LINE CARD REDUNDANCY ........................................................................................................................... 34
4.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 34
4.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 34
FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ......................................... 34
4.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 35
FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ........................................... 35
4.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 36
4.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36
FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ...................................................... 36
4.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 37
FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY ........................................................ 37
4.3 POWER FAILURE PROTECTION .................................................................................................................. 38
4.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38
4.5 NON-INTRUSIVE MONITORING .................................................................................................................... 38
FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION............................................................... 38
5.0 MICROPROCESSOR INTERFACE ......................................................................................................39
5.1 SERIAL MICROPROCESSOR INTERFACE BLOCK (BGA PACKAGE ONLY) ........................................... 39
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 39
5.1.1 SERIAL TIMING INFORMATION ................................................................................................................................ 39
FIGURE 29. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 39
5.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 40
5.1.3 ADDR[7:0] (SCLK1 - SCLK8) ..................................................................................................................................... 40
5.1.4 R/W (SCLK9)............................................................................................................................................................... 40
5.1.5 DUMMY BITS (SCLK10 - SCLK16) ............................................................................................................................ 40
5.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 40
5.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 40
FIGURE 30. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 41
TABLE 9: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) .................................. 41
5.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 42
TABLE 10: SELECTING THE MICROPROCESSOR INTERFACE MODE ................................................................................................... 42
FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK .................................................................. 42
5.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 43
TABLE 11: XRT83VSH28 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH INTEL AND MOTOROLA MODES
43
TABLE 12: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS .................................................................................................... 43
TABLE 13: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ........................................................................................... 44
5.4 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 45
FIGURE 32. INTEL P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ............................................ 46
TABLE 14: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS ........................................................................................ 46
5.5 MOTOROLA MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................... 47
FIGURE 33. MOTOROLA 68K P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS............................ 48
TABLE 15: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS........................................................................ 48
5.6 POWERPC 403 SYNCHRONOUS MODE: ..................................................................................................... 49
FIGURE 34. POWERPC 403 MODE TIMING - WRITE OPERATION...................................................................................................... 49
TABLE 16 POWER PC403 MODE TIMING - WRITE OPERATION......................................................................................................... 49
FIGURE 35. POWERPC 403 MODE TIMING - READ OPERATION ....................................................................................................... 50
TABLE 17 POWER PC403 MODE TIMING - READ OPERATION .......................................................................................................... 50
5.7 MICROPROCESSOR INTERFACE TIMING - MCP860 SYNCHRONOUS MODE ........................................ 51
FIGURE 36. MPC86X MODE TIMING - WRITE OPERATION............................................................................................................... 51
TABLE 18 MPC86X MODE TIMING - WRITE OPERATION.................................................................................................................. 51
TABLE 19 MPC86X TIMING INFORMATION - READ OPERATION ........................................................................................................ 52
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