參數(shù)資料
型號： XRT86VL32_07
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 117/174頁
文件大小： 903K
代理商： XRT86VL32_07
XRT86VL32
112
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
3
OOF ENB
R/W
0
Change in Out of Frame Defect Condition interrupt enable
This bit permits the user to either enable or disable the “Change in Out of
Frame Defect Condition” Interrupt, within the XRT86VL32 device. If the
user enables this interrupt, then the Receive E1 Framer block will generate
an interrupt in response to either one of the following conditions.
1.
The instant that the Receive E1 Framer block declares the Out of
Frame defect condition.
2.
The instant that the Receive E1 Framer block clears the Out of
Frame defect condition.
0 – Disables the “Change in Out of Frame Defect Condition” Interrupt.
1 – Enables the “Change in Out of Frame Defect Condition” Interrupt.
2
FMD ENB
R/W
0
Frame Mimic Detection Interrupt Enable
This bit permits the user to either enable or disable the “Frame Mimic
Detection” Interrupt, within the XRT86VL32 device. If the user enables this
interrupt, then the Receive E1 Framer block will generate an interrupt
when it detects the presence of Frame mimic bits (i.e., the payload bits
have appeared to mimic the framing bit pattern within the incoming E1
data stream).
0 – Disables the “Frame Mimic Detection” Interrupt.
1 – Enables the “Frame Mimic Detection” Interrupt.
1
SE_ENB
R/W
0
Synchronization Bit (CRC-4) Error Interrupt Enable
This bit permits the user to either enable or disable the “CRC-4 Error
Detection” Interrupt, within the XRT86VL32 device. If the user enables this
interrupt, then the Receive E1 Framer block will generate an interrupt
when it detects a CRC-4 error within the incoming E1 sub-multiframe.
0 – disable the “CRC-4 Error Detection” Interrupt.
1 – enable the “CRC-4 Error Detection” Interrupt.
0
FE_ENB
R/W
0
Framing Bit Error Interrupt Enable
This bit permits the user to either enable or disable the “Framing Alignment
Bit Error Detection” Interrupt, within the XRT86VL32 device. If the user
enables this interrupt, then the Receive E1 Framer block will generate an
interrupt when it detects one or more Framing Alignment Bit error within
the incoming E1 data stream.
0 – disable the “Framing Alignment Bit Error Detection” Interrupt.
1 – enable the “Framing Alignment Bit Error Detection” Interrupt.
N
OTE
:
Detecting Framing Alignment Bit Error doesn't not necessarily
indicate that synchronization has been lost.
T
ABLE
98: F
RAMER
I
NTERRUPT
E
NABLE
R
EGISTER
(FIER) H
EX
A
DDRESS
: 0
X
nB05
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
相關(guān)PDF資料
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參數(shù)描述
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XRT86VL32IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 2 IND FULL DPLX FIFO TWO-FRAME, CAS, CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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XRT86VL34 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL34_07 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
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