XRT86VL32
155
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
5
FLS_n
RO
0
FIFO Limit Status:
This READ-ONLY bit indicates whether or not the XRT86VL32 is
currently declaring the FIFO Limit Status.
This bit is set to a “1” to indicate that the jitter attenuator Read/Write
FIFO pointers are within +/- 3 bits.
0 = Indicates that the XRT86VL32 is NOT currently declaring the
FIFO Limit Status.
1 = Indicates that the XRT86VL32 is currently declaring the FIFO
Limit Status.
N
OTE
:
If the FIFO Limit Status Interrupt is enabled, (FLSIE bit - bit
D5 of register 0x0Fn4), any transition on this bit will
generate an Interrupt.
4
Reserved
-
0
This Bit Is Not Used
3
NLCD_n
RO
0
Network Loop-Code Detection Status Bit:
This bit operates differently in the Manual or the Automatic Network
Loop-Code detection modes.
Manual Loop-Up Code detection mode
(.i.e If NLCDE1 = “0” and NLCDE0 = “1”), this bit gets set to “1” as
soon as the Loop-Up Code (“00001”) is detected in the receive data
for longer than 5 seconds.
This bit stays high as long as the Receive E1 LIU Block detects the
presence of the Loop-Up code in the receive data and it is reset to
“0” as soon as it stops receiving the Loop-Up Code.
If the NLCD interrupt is enabled, the XRT86VL32 will initiate an
interrupt on every transition of the NLCD status bit.
Manual Loop-Down Code detection mode
(i.e., If NLCDE1 = “1” and NLCDE0 = “0”), this bit gets set to “1” as
soon as the Loop-Down Code (“001”) is detected in the receive data
for longer than 5 seconds.
This bit stays high as long as the Receive E1 LIU Block detects the
presence of the Loop-Down code in the receive data and it is reset
to “0” as soon as it stops receiving the Loop-Down Code.
If the NLCD interrupt is enabled, the XRT86VL32 will initiate an
interrupt on every transition of the NLCD status bit.
Automatic Loop-code detection mode
(i.e., If NLCDE1 = “1” and NLCDE0 =”1”), the state of the NLCD sta-
tus bit is reset to “0” and the XRT86VL32 is programmed to monitor
the receive input data for the Loop-Up code.
This bit is set to a “1” to indicate that the Network Loop Code is
detected for more than 5 seconds. Simultaneously the Remote
Loop-Back condition is automatically activated and the XRT86VL32
is programmed to monitor the receive data for the Network Loop
Down code. The NLCD bit stays ‘high’ as long as the Remote Loop-
Back condition is in effect even if the chip stops receiving the Loop-
Up code. Remote Loop-Back is removed only if the XRT86VL32
detects the Loop-Down Code “001” pattern for longer than 5 sec-
onds in the receive data. Upon detecting the Loop-Down Code “001”
pattern, the XRT86VL32 will reset the NLCD status bit and an inter-
rupt will be generated if the NLCD interrupt enable bit is enabled.
Users can monitor the state of this bit to determine if the Remote
Loop-Back is activated.
T
ABLE
121: LIU C
HANNEL
C
ONTROL
S
TATUS
R
EGISTER
(LIUCCSR) H
EX
A
DDRESS
: 0
X
0F
N
5
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION