參數(shù)資料
型號： XRT86VL32_07
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 25/174頁
文件大?。?/td> 903K
代理商： XRT86VL32_07
XRT86VL32
20
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
4
Transmit Frame Sync
Select
R/W
0
Transmit Frame Sync Select
This bit permits the user to configure the System-Side Terminal
Equipment or the E1 Transmit Framer to dictate whenever the Trans-
mit E1 Framer block will initiate its generation and transmission of
the very next E1 frame. If the system side controls, then all of the fol-
lowing will be true.
1. The corresponding TxSync_n and TxMSync_n pins will function
as input pins.
2. The Transmit E1 Framer block will initiate its generation of a new
E1 frame whenever it samples the corresponding “TxSync_n” input
pin “high” (via the TxSerClk_n input clock signal).
3. The Transmit E1 Framer block will initiate its generation of a new
CRC Multiframe whenever it samples the corresponding
“TxMSync_n” input pin “high”.
This bit can also be used to select the direction of the transmit single
frame boundary (TxSYNC) and multi-frame boundary (TxMSYNC)
depending on whether TxSERCLK is chosen as the timing source for
the transmit section of the framer. (CSS[1:0] = 01 in register 0xn100)
If TxSERCLK is chosen as the timing source:
0 = Configures TxSYNC and TxMSYNC as inputs. (System Side
Controls)
1 = Configures TxSYNC and TxMSYNC as outputs. (Chip Controls)
If either Recovered Line Clock, MCLK PLL is chosen as the tim-
ing source:
0 = Configures TxSYNC and TxMSYNC as outputs. (Chip Controls)
1 = Configures TxSYNC and TxMSYNC as inputs. (System Side
Controls)
N
OTE
:
TxSERCLK is chosen as the transmit clock if CSS[1:0] of the
Clock Select Register (Register Address: 0xn100) is set to
b01. Recovered Clock is chosen as the transmit clock if
CSS[1:0] is set to b00 or b11; Internal Clock is chosen as the
transmit clock if CSS[1:0] is set to b10.
3-2
Data Link Source
Select [1:0]
R/W
00
Data Link Source Select
These bits are used to specify the source of the Data Link bits that
will be inserted in the outbound E1 frames. The table below
describes the three different sources from which the Data Link bits
can be inserted.
T
ABLE
6: S
YNCHRONIZATION
MUX R
EGISTER
(SMR) H
EX
A
DDRESS
: 0
X
n109
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
DLSRC[1:0]
S
OURCE
OF
D
ATA
L
INK
BITS
00/11
TxSER Input - The transmit serial input from the
transmit payload data input block will be the
source for data link bits
01
Transmit HDLC Controller - The Transmit HDLC
Controller will generate either BOS (Bit Oriented
Signaling) or MOS (Message Oriented Signaling)
messages which will be inserted into the Data Link
bits in the outbound E1frames.
10
TxOH Input - The Transmit Overhead data Input
Port will be the source for the Data Link bits.
相關PDF資料
PDF描述
XRT86VL32IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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