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參數(shù)資料
| 型號(hào)： | XRT86VL38_1 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 24/66頁(yè) |
| 文件大小： | 425K |
| 代理商： | XRT86VL38_1 |
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XRT86VL38
21
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
TxCHN0_1/
TxFrTD0
TxCHN1_1/
TxFrTD1
TxCHN2_1/
TxFrTD2
TxCHN3_1/
TxFrTD3
TxCHN4_1/
TxFrTD4
TxCHN5_1/
TxFrTD5
TxCHN6_1/
TxFrTD6
TxCHN7_1/
TxFrTD7
B12
D18
D25
L25
AF22
AD15
AF9
AD3
A11
D15
E20
K17
U15
AB12
AB5
V8
I/O
8
Transmit Time Slot Octet Identifier Output 1 (TxCHNn_1) /
Transmit Serial Fractional Input (TxFrTDn):
The exact function of these pins depends on whether or not
the transmit framer enables the transmit fractional/signaling
interface, as described below:
If transmit fractional/signaling interface is disabled -
TxCHNn_1
These output signals (TxCHNn_4 through TxCHNn_0) reflect
the five-bit binary value of the current time slot being pro-
cessed by the transmit serial interface. Terminal Equipment
can use the TxCHCLK to sample the five output pins of each
channel in order to identify the time slot being processed. This
pin indicates Bit 1 of the time slot channel being processed.
If transmit fractional/signaling interface is enabled -
TxFrTDn
These pins are used as the fractional data input pins to input
fractional DS1/E1 payload data which will be inserted within
an outbound DS1/E1 frame. In this mode, terminal equipment
can use either TxCHCLK or TxSERCLK to clock in fractional
DS1/E1 payload data depending on the framer configuration.
N
OTES
:
1.
Transmit fractional/Signaling interface can be
enabled by programming to bit 4 - TxFr1544/
TxFr2048 bit from register 0xn120 to ‘1’.
2.
These 8 pins are internally pulled “Low” for each
channel.
TxCHN0_2/
Tx32MHz0
TxCHN1_2/
Tx32MHz1
TxCHN2_2/
Tx32MHz2
TxCHN3_2/
Tx32MHz3
TxCHN4_2/
Tx32MHz4
TxCHN5_2/
Tx32MHz5
TxCHN6_2/
Tx32MHz6
TxCHN7_2/
Tx32MHz7
A13
B19
C26
M22
AC20
AE15
AE9
AD2
D12
F15
F19
K22
Y16
W13
AA5
AB1
O
8
Transmit Time Slot Octet Identifier Output 2 (TxCHNn_2) /
Transmit 32.678MHz Clock Output (Tx32MHZ):
The exact function of these pins depends on whether or not
the transmit framer enables the transmit fractional/signaling
interface, as described below:
If transmit fractional/signaling interface is disabled -
TxCHNn_2
These output signals (TxCHNn_4 through TxCHNn_0) reflect
the five-bit binary value of the current time slot being pro-
cessed by the transmit serial interface. Terminal Equipment
can use the TxCHCLK to sample the five output pins of each
channel in order to identify the time slot being processed. This
pin indicates Bit 2 of the time slot channel being processed.
If transmit fractional/signaling interface is enabled -
Tx32MHz
These pins are used to output a 32.678MHz clock reference
which is derived from the MCLKIN input pin.
N
OTE
:
Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
TRANSMIT SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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| XRT86VL38ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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