參數(shù)資料
型號(hào)： XRT86VL38_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 33/66頁
文件大小： 425K
代理商： XRT86VL38_1
XRT86VL38
30
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RxCHN0_0/
RxSig0
RxCHN1_0/
RxSig1
RxCHN2_0/
RxSig2
RxCHN3_0/
RxSig3
RxCHN4_0/
RxSig4
RxCHN5_0/
RxSig5
RxCHN6_0/
RxSig6
RxCHN7_0/
RxSig7
D8
D14
A22
G26
AD25
AD18
AC13
AB8
A7
B13
B19
H19
AA22
U14
AA10
Y7
O
8
Receive Time Slot Octet Identifier Output (RxCHNn_0)
/ Receive Serial Signaling Output (RxSIGn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/sig-
naling interface, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_0:
These output pins (RxCHNn_4 through RxCHNn_0)
reflect the five-bit binary value of the current time slot
being output by the receive serial interface. System
equipment can use the RxCHCLKn to sample the five out-
put pins of each channel to identify the time slot being out-
put on these pins. RxCHNn_0 indicates the Least
Significant Bit (LSB) of the time slot channel being output.
If receive fractional/signaling interface is enabled -
RxSIGn:
These pins can be used to output robbed-bit signaling
data within an inbound DS1 frame or to output Channel
Associated Signaling (CAS) data within an inbound E1
frame, as described below.
T1 Mode:
Signaling data (A,B,C,D) of each channel will
be output on bit 4,5,6,7 of each time slot on the RxSIG pin
if 16-code signaling is used. If 4-code signaling is
selected, signaling data (A,B) of each channel will be out-
put on bit 4, 5 of each time slot on the RxSIG pin. If 2-
code signaling is selected, signaling data (A) of each
channel will be output on bit 4 of each time slot on the
RxSIG pin.
E1 Mode:
Signaling data in E1 mode will be output on the
RxSIGn pins on a time-slot-basis as in T1 mode, or it can
be output on time slot 16 only via the RxSIGn output pins.
In the latter case, signaling data (A,B,C,D) of channel 1
and channel 17 will be output on the RxSIGn pin during
time slot 16 of frame 1, signaling data (A,B,C,D) of chan-
nel 2 and channel 18 will be output on the RxSIGn pin
during time slot 16 of frame 2...etc. The CAS multiframe
Alignments bits (0000 bits) and the extra bits/alarm bit
(xyxx) will be output on the RxSIGn pin during time slot 16
of frame 0.
N
OTE
:
Receive Fractional/signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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XRT86VL38IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8 IND FULL DPLX FIFO TWO-FRAME CAS CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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