參數(shù)資料
型號: XRT86VL38_1
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 37/66頁
文件大?。?/td> 425K
代理商: XRT86VL38_1
XRT86VL38
34
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE LINE INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
D1
F1
H1
K1
M1
P1
T1
V1
G2
H2
K4
L2
M2
P3
T2
U4
I
-
Receive Positive Analog Input (RTIPn):
RTIP is the positive differential input from the line inter-
face. This input pin, along with the RRING input pin, func-
tions as the “Receive DS1/E1 Line Signal” input for the
XRT86VL38 device.
The user is expected to connect this signal and the
RRING input signal to a 1:1 transformer for proper opera-
tion. The center tap of the receive transformer should have
a bypass capacitor of 0.1
μ
F to ground (Chip Side) to
improve long haul application receive capabilities.
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
E1
G1
J1
L1
N1
R1
U1
W1
G3
H1
K3
L1
M1
P2
T3
U3
I
-
Receive Negative Analog Input (RRINGn):
RRING is the negative differential input from the line inter-
face. This input pin, along with the RTIP input pin, func-
tions as the “Receive DS1/E1 Line Signal” input for the
XRT86VL38 device.
The user is expected to connect this signal and the RTIP
input signal to a 1:1 transformer for proper operation. The
center tap of the receive transformer should have a
bypass capacitor of 0.1
μ
F to ground (Chip Side) to
improve long haul application receive capabilities.
RxLOS_0
RxLOS_1
RxLOS_2
RxLOS_3
RxLOS_4
RxLOS_5
RxLOS_6
RxLOS_7
E8
A16
B20
H24
AC26
AF20
AC12
AD4
C8
C14
D16
F22
W21
W15
Y10
U8
O
4
Receive Loss of Signal Output Indicator (RLOSn):
The XRT86VL38 device will assert this output pin (i.e.,
toggle it “high”) anytime (and for the duration that) the
Receive DS1/E1 Framer or LIU block declares the LOS
defect condition.
Conversely, the XRT86VL38 device will negate this output
pin (i.e., toggle it “l(fā)ow”) anytime (and for the duration that)
the Receive DS1/E1 Framer or LIU block is NOT declaring
the LOS defect condition.
This output pin will toggle “High” (declare LOS) if the
Receive Framer or the Receive LIU block associated with
Channel N determines that an RLOS condition occurs. In
other words, this pin is OR-ed with the LIU RLOS and the
Framer RLOS bit. If either the LIU RLOS or the Framer
RLOS bit associated with channel N pulses high, the cor-
responding RLOS pin of that particular channel will be set
to “High”.
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