參數(shù)資料
型號： XRT86VL38_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 28/66頁
文件大小： 425K
代理商： XRT86VL38_1
XRT86VL38
25
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
RECEIVE OVERHEAD INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
RxOH0
RxOH1
RxOH2
RxOH3
RxOH4
RxOH5
RxOH6
RxOH7
C11
B15
D21
F26
AA22
AE17
AE14
AF7
D11
A14
D18
H18
V18
Y14
U12
V10
O
8
Receive Overhead Output (RxOHn):
These pins function as the Receive Overhead output, or
Receive Signaling Output depending on the receive
framer configuration, as described below.
DS1 Mode
If the RxOH pins have been configured as the destina-
tion for the Data Link bits within an inbound DS1 frame,
datalink bits will be output to the RxOHn pins at either
2kHz or 4kHz depending on the Receive datalink band-
width selected. (Register 0xn10C).
If configured appropriately, signaling information in the
receive signaling array registers (Registers 0xn500-
0xn51F) can also be output to the RxOHn output pins.
E1 Mode
These output pins will always output the contents of the
National Bits (Sa4 through Sa8) if these Sa bits have
been configured to carry Data Link information (Register
0xn10C). The Receive Overhead Output Interface will
provide a clock edge on RxOHCLKn for each Sa bit car-
rying Data Link information.
If configured appropriately, signaling information in the
receive signaling array registers (Registers 0xn500-
0xn51F) can also be output to the RxOHn output pins.
RxOHCLK0
RxOHCLK1
RxOHCLK2
RxOHCLK3
RxOHCLK4
RxOHCLK5
RxOHCLK6
RxOHCLK7
B9
D16
E21
G24
Y22
AF17
AE13
AE7
F11
D14
A21
E22
V19
AA14
AB10
Y6
O
8
Receive Overhead Clock Output (RxOHCLKn):
This pin functions as an overhead output clock signal for
the receive overhead interface, and its function is
explained below.
DS1 Mode
If the RxOH pins have been configured to be the desti-
nation for Datalink bits, the DS1 transmit framer will out-
put a clock edge for each Data Link Bit. In DS1 ESF
mode, the RxOHCLK can either be a 2kHz or 4kHz out-
put signal depending on the selection of Data Link
Bandwidth (Register 0xn10C).
Data Link Equipment can clock out datalink bits on the
RxOHn pin using this clock signal.
E1 Mode
The E1 receive framer provides a clock edge for each
National Bit (Sa bits) that is configured to carry data link
information.
Data Link Equipment can clock out datalink bits on the
RxOHn pin using this clock signal.
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