參數(shù)資料
型號(hào)： XRT86VL38_1
廠商： Exar Corporation
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 35/66頁(yè)
文件大小： 425K
代理商： XRT86VL38_1
XRT86VL38
32
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RxCHN0_3/
Rx8KHZ0
RxCHN1_3/
Rx8KHZ1
RxCHN2_3/
Rx8KHZ2
RxCHN3_3/
Rx8KHZ3
RxCHN4_3/
Rx8KHZ4
RxCHN5_3/
Rx8KHZ5
RxCHN6_3/
Rx8KHZ6
RxCHN7_3/
Rx8KHZ7
C10
B16
C23
J26
AC23
AC17
AD12
AE5
E11
A15
D19
H21
AB22
V14
AB8
AA3
O
8
Receive Time Slot Octet Identifier Output-Bit 3
(RxCHNn_3) / Receive 8KHz Clock Output (Rx8KHZn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/sig-
naling interface, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_3:
These output pins (RxCHNn_4 through RxCHNn_0)
reflect the five-bit binary value of the current time slot
being output by the receive serial interface. System
equipment can use the RxCHCLKn to sample the five out-
put pins of each channel to identify the time slot being out-
put on these pins. RxCHNn_3 indicates Bit 3 of the time
slot channel being output.
If receive fractional/signaling interface is enabled -
Rx8KHZn:
These pins output a reference 8KHz clock signal derived
from the MCLKIN input.
N
OTE
:
Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
RxCHN0_4/
RxSCLK0
RxCHN1_4/
RxSCLK1
RxCHN2_4/
RxSCLK2
RxCHN3_4/
RxSCLK3
RxCHN4_4/
RxSCLK4
RxCHN5_4/
RxSCLK5
RxCHN6_4/
RxSCLK6
RxCHN7_4/
RxSCLK7
A10
C17
A26
K25
AB22
AD17
AF11
AF3
B10
F16
B21
J22
Y19
W14
AB7
W7
O
8
Receive Time Slot Octet Identifier Output-Bit 4
(RxCHNn_4) / Receive Recovered Line Clock Output
(RxSCLKn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/sig-
naling interface, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_4:
These output pins (RxCHNn_4 through RxCHNn_0)
reflect the five-bit binary value of the current time slot
being output by the receive serial interface. System
equipment can use the RxCHCLKn to sample the five out-
put pins of each channel to identify the time slot being out-
put on these pins. RxCHNn_4 indicates the Most
Significant Bit (MSB) of the time slot channel being out-
put.
If receive fractional/signaling interface is enabled -
Receive Recovered Line Clock Output (RxSCLKn):
These pins output the recovered T1/E1 line clock
(1.544MHz in T1 mode and 2.048MHz in E1 mode) for
each channel.
N
OTE
:
Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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