參數(shù)資料
型號： XRT86VL38_2
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 103/160頁
文件大小： 860K
代理商： XRT86VL38_2
XRT86VL38
98
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
T
ABLE
84: F
RAMER
I
NTERRUPT
S
TATUS
R
EGISTER
(FISR) H
EX
A
DDRESS
: 0
X
nB04
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-6
-
-
-
Reserved (For E1 mode only)
5
SIG
RUR/
WC
0
Change in Signaling Bits Interrupt Status
This Reset-Upon-Read bit field indicates whether or not the “Change in
Signaling Bits” interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will generate
an interrupt whenever any one of the four signaling bits values (A,B,C,D)
has changed in any one of the 24 channels within the incoming T1
frames. Users can read the signaling change registers (address 0xn10D-
0xn10F) to determine which signalling channel has changed.
0 = Indicates that the “Change in Signaling Bits” interrupt has not occurred
since the last read of this register.
1 = Indicates that the “Change in Signaling Bits” interrupt has occurred
since the last read of this register.
N
OTE
:
This bit only has meaning when Robbed-Bit Signaling is enabled.
4
COFA
RUR/
WC
0
Change of Frame Alignment (COFA) Interrupt Status
This Reset-Upon-Read bit field indicates whether or not the “Change of
Framing Alignment (COFA)” interrupt has occurred since the last read of
this register. If this interrupt is enabled, then the Receive T1 Framer block
will generate an interrupt whenever the Receive T1 Framer block detects
a Change of Framing Alignment Signal (e.g., the Framing bits have
appeared to move to a different location within the incoming T1 data
stream).
0 = Indicates that the “Change of Framing Alignment (COFA)” interrupt
has not occurred since the last read of this register.
1 = Indicates that the “Change of Framing Alignment (COFA)” interrupt
has occurred since the last read of this register.
3
LOF_Status
RUR/
WC
0
Change in Receive Loss of Frame Condition Interrupt Status
.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive Loss of Frame Condition” interrupt has occurred since the last
read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will generate
an interrupt in response to either one of the following conditions.
1.
Whenever the Receive T1 Framer block declares the Loss of
Frame condition.
2.
Whenever the Receive T1 Framer block clears the Loss of Frame
condition
0 = Indicates that the “Change in Receive Loss of Frame condition” inter-
rupt has not occurred since the last read of this register
1 = Indicates that the “Change in Receive Loss of Frame condition” inter-
rupt has occurred since the last read of this register
相關(guān)PDF資料
PDF描述
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB484 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT86VL38IB484-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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