參數(shù)資料
型號： XRT86VL38_2
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 147/160頁
文件大?。?/td> 860K
代理商： XRT86VL38_2
XRT86VL38
142
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
N
OTE
:
Register 0x0F
N
4, 0x0F
N
5 and 0x0F
N
6 only work if the LIU is placed in Single Rail mode. If done so, the Framer
block must also be placed in Single Rail mode in Register 0xn101.
1
RLOSIS_n
RUR/
WC
0
Change of Receive LOS (Loss of Signal) Defect Condition Inter-
rupt Status:
This RESET-upon-READ bit indicates whether or not the “Change of
the Receive LOS Defect Condition” Interrupt has occurred since the
last read of this register.
0 = Indicates that the “Change of the Receive LOS Defect Condi-
tion” Interrupt has NOT occurred since the last read of this register.
1 - Indicates that the “Change of the Receive LOS Defect Condition”
Interrupt has occurred since the last read of this register.
N
OTE
:
The user can determine the current state of the “Receive
LOS Defect condition” by reading out the contents of Bit 1
(Receive LOS Defect Condition Status) within Register
0xnFn5.
0
QRPDIS_n
RUR/
WC
0
Change in Quasi-Random Pattern Detection Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “Change in
QRSS Pattern Detection” Interrupt has occurred since the last read
of this register.
0 = Indicates that the “Change in QRSS Pattern Detection” Interrupt
has NOT occurred since the last read of this register.
1 = Indicates that the “Change in QRSS Pattern Detection” Interrupt
has occurred since the last read of this register.
This bit is set to a “1” every time when QRPD status bit (bit 0 of Reg-
ister 0x0Fn5) has changed since the last read of this register.
N
OTE
:
Users can determine the current state of the “QRSS Pattern
Detection” by reading out the content of bit 0 within Register
0x0Fn5
T
ABLE
116: LIU C
HANNEL
C
ONTROL
C
ABLE
L
OSS
R
EGISTER
(LIUCCCCR) H
EX
A
DDRESS
: 0
X
0F
N
7
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
RO
0
6
Reserved
RO
0
5-0
CLOS[5:0]
RO
0
Cable Loss [5:0]:
These bits represent the six bit receive selective equalizer setting
which is also a binary word that represents the cable attenuation
indication within ±1dB.
CLOS5_n is the most significant bit (MSB) and CLOS0_n is the
least significant bit (LSB).
T
ABLE
115: LIU C
HANNEL
C
ONTROL
I
NTERRUPT
S
TATUS
R
EGISTER
(LIUCCISR) H
EX
A
DDRESS
: 0
X
0F
N
6
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
相關(guān)PDF資料
PDF描述
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB484 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT86VL38ES484 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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XRT86VL38IB484 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8 IND FULL DPLX FIFO TWO-FRAME CAS CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38IB484-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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