參數(shù)資料
型號(hào): XRT86VL38_2
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 148/160頁
文件大小: 860K
代理商: XRT86VL38_2
XRT86VL38
143
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
117: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
1 (LIUCCAR1) H
EX
A
DDRESS
: 0
X
0F
N
8
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
R/W
0
6-0
Arb_Seg1
R/W
0
Arbitrary Transmit Pulse Shape, Segment 1:
These seven bits form the first of the eight segments of the transmit
shape pulse when the XRT86VL38 is configured in “Arbitrary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
N
OTE
:
Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
T
ABLE
118: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
2 (LIUCCAR2) H
EX
A
DDRESS
: 0
X
0F
N
9
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
R/W
0
6-0
Arb_Seg2
R/W
0
Arbitrary Transmit Pulse Shape, Segment 2
These seven bits form the second of the eight segments of the
transmit shape pulse when the XRT86VL38 is configured in “Arbi-
trary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
N
OTE
:
Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
T
ABLE
119: LIU C
HANNEL
C
ONTROL
A
RBITRARY
R
EGISTER
3 (LIUCCAR3) H
EX
A
DDRESS
: 0
X
0F
N
A
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
R/W
0
6-0
Arb_seg3
R/W
0
Arbitrary Transmit Pulse Shape, Segment 3
These seven bits form the third of the eight segments of the transmit
shape pulse when the XRT86VL38 is configured in “Arbitrary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
N
OTE
:
Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
相關(guān)PDF資料
PDF描述
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB484 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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