XRT86VL38
101
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.1
T
ABLE
87: PMON LAPD F
RAME
C
HECK
S
EQUENCE
E
RROR
C
OUNTER
1 (LFCSEC1) H
EX
A
DDRESS
: 0
X
n90C
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
FCSEC1[7]
RUR
0
Performance Monitor - LAPD 1 Frame Check Sequence Error
Counter (8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Frame Check Sequence Error have been detected by
the LAPD Controller 1 since the last read of this register.
6
FCSEC1[6]
RUR
0
5
FCSEC1[5]
RUR
0
4
FCSEC1[4]
RUR
0
3
FCSEC1[3]
RUR
0
2
FCSEC1[2]
RUR
0
1
FCSEC1[1]
RUR
0
0
FCSEC1[0]
RUR
0
T
ABLE
88: PMON PRBS B
IT
E
RROR
C
OUNTER
MSB (PBECU) H
EX
A
DDRESS
: 0
X
n90D
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
PRBSE[15]
RUR
0
Performance Monitor - E1 PRBS Bit Error 16-Bit Counter -
Upper Byte:
These RESET-upon-READ bits, along with that within the “PMON
E1 PRBS Bit Error Counter Register LSB” combine to reflect the
cumulative number of instances that the ReceiveE1 PRBS Bit errors
has been detected by the Receive E1 Framer block since the last
read of this register.
This register contains the Most Significant byte of this 16-bit of the
Receive E1 PRBS Bit Error counter.
N
OTE
:
For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
PRBSE[14]
RUR
0
5
PRBSE[13]
RUR
0
4
PRBSE[12]
RUR
0
3
PRBSE[11]
RUR
0
2
PRBSE[10]
RUR
0
1
PRBSE[9]
RUR
0
0
PRBSE[8]
RUR
0
T
ABLE
89: PMON PRBS B
IT
E
RROR
C
OUNTER
LSB (PBECL) H
EX
A
DDRESS
: 0
X
n90E
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
PRBSE[7]
RUR
0
Performance Monitor - E1 PRBS Bit Error 16-Bit Counter -
Lower Byte:
These RESET-upon-READ bits, along with that within the “PMON
E1 PRBS Bit Error Counter Register MSB” combine to reflect the
cumulative number of instances that the ReceiveE1 PRBS Bit errors
has been detected by the Receive E1 Framer block since the last
read of this register.
This register contains the Least Significant byte of this 16-bit of the
Receive E1 PRBS Bit Error counter.
N
OTE
:
For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
PRBSE[6]
RUR
0
5
PRBSE[5]
RUR
0
4
PRBSE[4]
RUR
0
3
PRBSE[3]
RUR
0
2
PRBSE[2]
RUR
0
1
PRBSE[1]
RUR
0
0
PRBSE[0]
RUR
0