XRT86VL38
122
REV. V1.2.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
4
CAS SYNC
RO
0
CAS Multiframe Alignment is in SYNC
This READ ONLY bit field indicates whether or not the E1 Receive Framer
Block is declaring CAS Multiframe Alignment LOCK status.
The E1 Receive Framer Block will declare the CAS Multiframe Alignment
LOCK status according to the CAS Multiframe Alignment Algorithm as
described in the Framing Select Register (FSR - address 0xn107).
The E1 Receive Framer Block will declare the CAS Multiframe Alignment
LOSS OF LOCK status when CASC number of consecutive CAS Multi-
frame Alignment Signals have been received in error, where CASC sets
the Loss of CAS Multiframe Alignment Criteria, as described in the Fram-
ing Control Register (FCR - address 0xn10B).
0 = Indicates that the E1 Receive Framer Block is currently declaring CAS
Multiframe LOSS OF LOCK status
1 = Indicates that the E1 Receive Framer Block is currently declaring CAS
Multiframe LOCK status
N
OTE
:
In E1 mode, this bit has no meaning if Channel Associated
Signaling is disabled.
3
CRCMLOCK
RO
0
CRC Multiframe is in SYNC
This READ ONLY bit field indicates whether or not the E1 Receive Framer
Block is declaring the E1 CRC Multiframe Alignment LOCK status.
The E1 Receive Framer declares the CRC Multiframe Alignment LOCK
status according to the CRC Multiframe Alignment Declaration Criteria
which can be selected in the Framing Select Register (FSR - address
0xn107)
The E1 Receive Framer declares the CRC Multiframe Alignment LOSS
OF LOCK status according to the Loss CRC Multiframe Alignment Criteria
selected in the Framing Control Register (FCR - address 0xn10B)
0 = Indicates that the E1 Receive Framer is currently declaring E1 CRC
Multiframe Alignment LOSS OF LOCK status
0 = Indicates that the E1 Receive Framer is currently declaring E1 Multi-
frame Alignment LOCK status
N
OTE
:
In E1 mode, this bit has no meaning if CRC Multiframe Alignment
is disabled.
2
RxSB_FULL
RUR/
WC
0
Receive Slip buffer Full Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Receive Slip Buffer
Full interrupt has occurred since the last read of this register. The Receive
Slip Buffer Full interrupt is declared when the receive slip buffer is filled. If
the receive slip buffer is full and a WRITE operation occurs, then a full
frame of data will be deleted, and this interrupt bit will be set to ‘1’.
0 = Indicates that the Receive Slip Buffer Full interrupt has not occurred
since the last read of this register.
1 = Indicates that the Receive Slip Buffer Full interrupt has occurred since
the last read of this register.
T
ABLE
103: S
LIP
B
UFFER
I
NTERRUPT
S
TATUS
R
EGISTER
(SBISR) H
EX
A
DDRESS
: 0
X
nB08
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION