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參數(shù)資料
| 型號(hào)： | XRT86VL38IB484 |
| 廠商： | EXAR CORP |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | DATACOM, FRAMER, PBGA484 |
| 封裝： | 23 X 23 MM, BGA-484 |
| 文件頁(yè)數(shù)： | 26/183頁(yè) |
| 文件大小： | 929K |
| 代理商： | XRT86VL38IB484 |
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XRT86VL38
21
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.1
0
FAS Frame Align
Sel
R/W
0
FAS Alignment Declaration Algorithm Select
This bit specifies which algorithm the Receive E1 Framer block uses in its
search for the FAS Alignment.
0 = Selects the FAS Alignment Algorithm 1
1 = Selects the FAS Alignment Algorithm 2
FAS Alignment Algorithm 1
If the Receive E1 Framer block has been configured to use “FAS Alignment
Algorithm # 1", then it will acquire FAS alignment by performing the follow-
ing three steps:
Step 1
- The Receive E1 Framer block begins by searching for the correct
7-bit FAS pattern. Go to Step 2 if found.
Step 2
- Check if the FAS is absent in the following frame by verifying that
bit 2 of the assumed timeslot 0 of the Non-FAS frame is a one. Go back to
Step 1 if failed, otherwise, go to step 3.
Step 3
- Check if the FAS is present in the assumed timeslot 0 of the third
frame. Go back to Step 1 if failed.
After the first three steps (if they all passed), the Receive E1 Framer Block
will declare FAS in SYNC if Frame Check Sequence (Bit 1 of this register) is
disabled. If Frame Check Sequence (Bit 1 of this register) is enabled, then
the Receive E1 Framer Block will need to verify the correct frame alignment
for an additional two frames.
FAS Alignment Algorithm 2
If the Receive E1 Framer block has been configured to support “FAS Align-
ment Algorithm # 2, then it will perform the following 3 steps in order to
acquire and declare FAS Frame Alignment with the incoming E1 data-
stream. Algorithm 2 is similar to Algorithm 1 but adds a one-frame hold off
time after the second step fails. After the second step fails, it waits for the
next assumed FAS in the next frame before it begins the new search for the
correct FAS pattern.
Step 1
- Algorithm 1 begins by searching for the correct 7-bit FAS pattern.
Go to Step 2 if found.
Step 2
- Check if the FAS is absent in the following frame by verifying that
bit 2 of the assumed timeslot 0 of the Non-FAS frame is a one. Go back to
Step 4 if failed, otherwise, go to step 3.
Step 3
- Check if the FAS is present in the assumed timeslot 0 of the third
frame. Go back to Step 1 if failed, otherwise, proceed to check for Frame
Check Sequence.
Step 4
- Wait for assumed FAS in the next frame, then go back to Step 1
After the first three steps (if they all passed), the Receive E1 Framer Block
will declare FAS in SYNC if Frame Check Sequence (Bit 1 of this register) is
disabled. If Frame Check Sequence (Bit 1 of this register) is enabled, then
the Receive E1 Framer Block will need to verify the correct frame alignment
for an additional two frames.
T
ABLE
6: F
RAMING
S
ELECT
R
EGISTER
(FSR) H
EX
A
DDRESS
: 0
X
n107
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL38_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL38 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL38_1 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL3x | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL3X_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL38IB484-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86VL38IB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86VL38IB-F | 制造商:Exar Corporation 功能描述:T1/E1 Framer Combo IC |
| XRT86VL3X | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VL3X_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
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