參數(shù)資料
型號： XRT86VL3X_07
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 41/153頁
文件大小： 1316K
代理商： XRT86VL3X_07
XRT86VL3X
34
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
The Transmit Data Link Source Select bits of the Transmit Data Link Select Register (TDLSR) controls the
insertion of data link bits into the FDL bits in ESF framing format mode. The table below shows configuration of
the Transmit Data Link Source Select bits of the Transmit Data Link Select Register (TDLSR).
If the Transmit Data Link Source Select bits of the Transmit Data Link Select Register are set to 10, the
Transmit Overhead Input Interface Block becomes input source of the FDL bits.
The XRT86VL3x allows the user to select bandwidth of the Facility Data Link Channel in ESF framing format
mode. The FDL can be either a 4KHz or 2KHz data link channel. The Transmit Data Link Bandwidth Select bits
of the Transmit Data Link Select Register (TDLSR) determine the bandwidth of FDL channel in ESF framing
format mode.
The table below shows configuration of the Transmit Data Link Bandwidth Select bits of the Transmit Data Link
Select Register (TDLSR).)
Figure 35
below shows the timing diagram of the input and output signals associated with the DS1 Transmit
Overhead Input Interface module in ESF framing format mode.
TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (ADDRESS = 0XN10AH)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1-0
Transmit Data Link
Source Select
R/W
00 - The Facility Data Link bits are inserted into the framer through either
the LAPD controller or the SLC96 buffer.
01 - The Facility Data Link bits are inserted into the framer through the
Transmit Serial Data input Interface via the TxSer_n pins.
10 - The Facility Data Link bits are inserted into the framer through the
Transmit Overhead Input Interface via the TxOH_n pins.
11 - The Facility Data Link bits are forced to one by the framer.
TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (ADDRESS = 0XN10AH)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
5-4
Transmit Data Link
Bandwidth Select
R/W
00 - The Facility Data Link is a 4KHz channel. All available FDL bits (first
bit of every other frame) are used as data link bits.
01 - The Facility Data Link is a 2KHz channel. Only the odd FDL bits (first
bit of frame 1, 5, 9…) are used as data link bits.
10 - The Facility Data Link is a 2KHz channel. Only the even FDL bits (first
bit of frame 3, 7, 11…) are used as data link bits.
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