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參數(shù)資料
| 型號： | XRT86VL3X_07 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 72/153頁 |
| 文件大?。?/td> | 1316K |
| 代理商： | XRT86VL3X_07 |
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XRT86VL3X
65
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
The local Terminal Equipment maps four 2.048Mbit/s E1 data streams into this 16.384Mbit/s data stream as
described below:
1.
Payload data of four channels are repeated and grouped together in a byte-interleaved way. The first pay-
load bit of Timeslot 0 of Channel 0 is sent first, followed by the second payload bit of Timeslot 0 of Channel
0 and so on. After all the bits of Timeslot 0 of Channel 0 is sent repeatedly, the Terminal Equipment will
start sending the payload bits of Timeslot 0 of Channel 1 and 2. The payload bits of Timeslot 0 of Channel
3 are sent last.
After the payload bits of Timeslot 0 of all four channels are sent, it comes the payload bits of Timeslot 1 of
Channel 0 and so on. The table below demonstrates how payload bits of four channels are mapped into
one 16.384Mbit/s data stream
X
Y
: The Xth payload bit of Channel Y
2.
When the framer is running at HMVIP or H100 16.384MBit/s byte-mulitplexed mode, signaling information
is inserted from the TxSig/TSb[0] pin or from the TSCR register (0xn340-n35F).
When the local terminal is sending the fifth payload bit of one channel, signaling bit A of that
corresponding channel is repeated and sent through the TxSig/TSb[0] pin; Similarly, signaling bit B, C,
and D of the corresponding channel is repeated and sent through the TxSig/TSb[0] pin when the local
terminal is providing the sixth, seventh, and eighth payload bit respectively, as shown in
Figure 71
.
3.
After the first octet of all four channels are sent, the local Terminal Equipment start sending the second
octets following the same rules of Step 1 and 2.
For HMVIP mode, the Transmit Single-frame Synchronization signal should pulse HIGH for four clock cycles
(the last two bit positions of the previous multiplexed frame and the first two bits of the next multiplexed frame)
indicating frame boundary of the multiplexed data stream. For H100 mode, the Transmit Single-frame
Synchronization signal should pulse HIGH for two clock cycles (the last bit position of the previous multiplexed
frame and the first bit position of the next multiplexed frame). The Transmit Single-frame Synchronization
signal of Channel 0 pulses HIGH to identify the start of multiplexed data stream of Channel 0-3. The Transmit
Single-frame Synchronization signal of Channel 4 pulses HIGH to identify the start of multiplexed data stream
of Channel 4-7. By sampling the HIGH pulse on the Transmit Single-frame Synchronization signal, the framer
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
1
0
1
0
2
0
2
0
3
0
3
0
4
0
4
0
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
1
1
1
1
2
1
2
1
3
1
3
1
4
1
4
1
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
1
2
1
2
2
2
2
2
3
2
3
2
4
2
4
2
B
IT
0
B
IT
1
B
IT
2
B
IT
3
B
IT
4
B
IT
5
B
IT
6
B
IT
7
1
3
1
3
2
3
2
3
3
3
3
3
4
3
4
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL3X | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT91L30_0611 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
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