參數(shù)資料
型號(hào)： XRT91L32IQTR
廠商： Exar Corporation
文件頁(yè)數(shù)： 3/37頁(yè)
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 8BIT 100QFP
產(chǎn)品變化通告： XRT91L32IQ(TR) Obsolescence 12/Oct/2010
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 帶卷 (TR)
xr
XRT91L32
REV. 1.0.3
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
9
POWER AND GROUND
CAP1P
CAP2P
Analog
-
63
66
CDR Non-Inverting External Feeback Capacitor
C1 = 0.47
μF ± 10% tolerance
(Isolate from noise and place close to pin)
CAP1N
CAP2N
Analog
-
64
65
CDR Inverting External Feeback Capacitor
C2 = 0.47
μF ± 10% tolerance
(Isolate from noise and place close to pin)
DLOSDIS
LVTTL
I
17
LOS (Los of Signal) Detect Disable
Disables internal LOS monitoring and automatic muting of
RXDO[7:0] upon LOS detection (according to gating shown in
Figure 7.) LOS is declared when a string of 128 consecutive
zeros occur on the line. LOS condition is cleared when the 16
or more pulse transitions is detected for 128 bit period sliding
window.
"Low" = Monitor and Mute received data upon LOS declaration
"High" = Disable internal LOS monitoring (see Figure 7 for logic
operation.)
LOSEXT
SE-LVPECL
I
53
LOS or Signal Detect Input from Optical Module
Active "Low." When active, this pin can force the received data
output bus RXDO[7:0] to a logic state of ’0’ per Figure 7.
"Low" = Forced LOS
"High" = Normal Operation
NAME
TYPE
PIN
DESCRIPTION
VDD3.3
PWR
2,28,31,49,54,
58,76,99,81
3.3V CMOS Power Supply
VDD3.3 should be isolated from the analog VDD power supplies.
Use a ferrite bead along with an internal power plane separation.
The VDD3.3 power supply pins should have bypass capacitors to
the nearest ground. For best results, refer to Application notes
about general board layout guidelines.
AVDD3.3_TX
PWR
62
Analog 3.3V Transmitter Power Supply
AVDD3.3_TX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_TX power supply pins should
have bypass capacitors to the nearest ground.
AVDD3.3_RX
PWR
67,,68,69
Analog 3.3V Receiver Power Supply
AVDD3.3_RX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_RX power supply pins should
have bypass capacitors to the nearest ground.
VDD_LVPECL
PWR
9,15,21
3.3V Input/Output LVPECL Bus Power Supply
These pins require a 3.3V potential voltage for properly biasing
the Differential LVPECL input and output pins.
AGND_TX
PWR
59,60
Transmitter Analog Ground for 3.3V Analog Power Supplies
It is recommended that all ground pins of this device be tied
together.
NAME
LEVEL
TYPE
PIN
DESCRIPTION
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