參數(shù)資料
型號(hào)： XRT91L32IQTR
廠商： Exar Corporation
文件頁(yè)數(shù)： 5/37頁(yè)
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 8BIT 100QFP
產(chǎn)品變化通告： XRT91L32IQ(TR) Obsolescence 12/Oct/2010
標(biāo)準(zhǔn)包裝： 1,000
類型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 帶卷 (TR)
xr
XRT91L32
REV. 1.0.3
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
11
1.0
FUNCTIONAL DESCRIPTION
The XRT91L32 transceiver is designed to operate with a SONET Framer/ASIC device and provide a high-
speed serial interface to optical networks. The transceiver converts 8-bit parallel data running at 77.76 Mbps
(STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) to a serial Differential LVPECL bit stream at 622.08 Mbps or
155.52 Mbps and vice-versa. It implements a clock multiplier unit (CMU), SONET/SDH serialization/de-
serialization (SerDes), receive clock and data recovery (CDR) unit and a SONET/SDH frame and byte
boundary detection circuit. The transceiver is divided into Transmit and Receive sections and is used to
provide the front end component of SONET equipment, which includes primarily serial transmit and receive
functions.
1.1
STS-12/STM-4 and STS-3/STM-1 Mode of Operation
Functionality of the transceiver can be configured by using the appropriate signal level on the STS-12/STS-3
pin. STS-3/STM-1 mode is selected by pulling STS-12/STS-3 "Low" as described in the Hardware Pin
Descriptions. However, if STS-12/STM-4 mode is desired, it is selected by pulling STS-12/STS-3 "High."
Therefore, the following sections describe the functionality rather than how each function is controlled. Hence,
the hardware Pin and the Register Bit Descriptions focus on device configuration.
1.2
Clock Input Reference for Clock Multiplier (Synthesizer) Unit
The XRT91L32 can accept both a 19.44 MHz or a 77.76 MHz Differential LVPECL clock input at REFCLKP/N
or a Single-Ended LVTTL clock at TTLREFCLK as its internal timing reference for generating higher speed
clocks. The REFCLKP/N or TTLREFCLK input should be generated from an LVPECL/LVTTL crystal oscillator
which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the
necessary accuracy required for SONET systems. The reference clock can be provided with one of two
frequencies chosen by CMUFREQSEL. The reference frequency options for the XRT91L32 are listed in
Table 1.
1.3
Data Latency
Due to different operating modes and data logic paths through the device, there is an associated latency from
data ingress to data egress. Table 2 specifies the data latency for a typical path.
TABLE 2: DATA INGRESS TO DATA EGRESS LATENCY
TABLE 1: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED)
CMUFREQSEL
STS12/STS3
REFCLKP/N OR TTLREFCLK
REFERENCE FREQUENCY
DATA RATE
0
77.76 MHz
STS-3/STM-1
155.52 Mbps
0
1
77.76 MHz
STS-12/STM-4
622.08 Mbps
1
0
19.44 MHz
STS-3/STM-1
155.52 Mbps
1
19.44 MHz
STS-12/STM-4
622.08 Mbps
MODE OF
OPERATION
DATA PATH
CLOCK REFERENCE RANGE OF CLOCK
CYCLES
Thru-mode
MSB at RXIP/N to data on RXDO[7:0]
Recoved RXIP/N Clock
25 to 35
Serial Remote Loopback MSB at RXIP/N to MSB at TXOP/N
Recoved RXIP/N Clock
2 to 4
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