NOTE
參數(shù)資料
型號: XRT91L34IV
廠商: Exar Corporation
文件頁數(shù): 25/38頁
文件大?。?/td> 0K
描述: IC MULTIRATE CDR QUAD 128LQFP
標(biāo)準(zhǔn)包裝: 72
類型: 時鐘和數(shù)據(jù)恢復(fù)(CDR),扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: SONET/SDH,STS,STM
輸入: LVDS,LVPECL
輸出: LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
XRT91L34
31
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
NOTE: n denotes channel number.
TABLE 16: MICROPROCESSOR INTERFACE REGISTER 0X09, 0X11, 0X19, 0X21 BIT DESCRIPTION
CONFIGURATION AND INTERRUPT ENABLE CHANNEL REGISTER (CH0 = 0X09, CH1 = 0X11, CH2 = 0X19, CH3 = 0X21)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
RO
0
D6
Reserved
This Register Bit is Not Used
RO
0
D5
DATAnRATE1
Data Rate Selection Bit-1 and Bit-0
These bits selects SONET/SDH reception speed rate for each of
the four channels independently according to the logic below.
R/W
0
D4
DATAnRATE0
R/W
0
D3
Reserved
This Register Bit is Not Used
RO
0
D2
Reserved
This Register Bit is Not Used
RO
0
D1
LOLn_IE
Loss of Lock Interrupt Enable
"0" = Masks the LOL interrupt generation
"1" = Enables Interrupt generation
R/W
0
D0
LOSn_IE
Loss of Signal Interrupt Enable
"0" = Masks the LOS interrupt generation
"1" = Enables Interrupt generation
R/W
0
DATANRATE[1:0]
DATA RATE
0
STS-1/STM-0
51.84 Mbps
0
1
STS-3/STM-1
155.52 Mbps
1
0
STS-12/STM-4
622.08 Mbps
1
STS-12/STM-4
622.08 Mbps
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參數(shù)描述
XRT91L34IVF 制造商:Exar Corporation 功能描述:CDR 51.84Mbps/155.52Mbps/622.08Mbps SONET/SDH 128-Pin LQFP 制造商:EXAR 功能描述:CDR 51.84Mbps/155.52Mbps/622.08Mbps SONET/SDH 128-Pin LQFP
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