參數(shù)資料
型號: XRT91L34IV
廠商: Exar Corporation
文件頁數(shù): 9/38頁
文件大?。?/td> 0K
描述: IC MULTIRATE CDR QUAD 128LQFP
標(biāo)準(zhǔn)包裝: 72
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: SONET/SDH,STS,STM
輸入: LVDS,LVPECL
輸出: LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
XRT91L34
17
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
2.4
Internal Digital Loss of Signal and External Signal Detection
XRT91L34 has an integrated Digital Loss of Signal (DLOS) circuit and supports external Signal Detection
(SDEXT) for detecting and determining received signal integrity. The internal DLOS circuit monitors the
incoming data stream. If the incoming data stream has no transition for more than 2.5
s, Loss of Signal is
declared. This LOS condition will be cleared when the circuit detects transitions in a 128
s interval sliding
window. Pulling the DLOSDIS pin signal to a high level in hardware mode or setting DLOSDIS bit in host mode
will disable the internal DLOS detection circuit to permit the framer/mapper interface to determine the Loss of
Signal declaration and clearance criteria for specific applications. The external Signal Detect function is
supported by the SDEXT input. An LVCMOS/LVTTL signal comes from the optical module through an output
usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High." The
SDEXT and POL inputs are Exclusive OR’ed to determine external Loss of Signal (LOS) condition. In the event
that internal DLOS is detected or an external SDEXT input indicates signal absence, the recovered serial data
output will be forced to a logic state "0," and the LOS status register is set whenever the host mode serial
microprocessor interface is active. This acts as a receive data mute upon LOS function to prevent data
chattering and to prevent random noise from being misinterpreted as valid incoming data. Figure 7 shows the
Loss of Signal Detection logic circuit. Table 4 specifies LOS declaration polarity settings.
FIGURE 7. LOSS OF SIGNAL DECLARATION CIRCUIT
TABLE 4: EXTERNAL LOS DECLARATION POLARITY SETTING
SDEXT
POL
INTERNAL SIGNAL DETECT
LOS BIT STATE
(HOST MODE ONLY)
RXDO[3:0]P/N
0
Active Low. Optical signal presence
indicated by SDEXT logic 0 input from
optical module.
Low
Normal
Operation
0
1
Active High. Optical signal presence
indicated by SDEXT logic 1 input from
optical module.
High
LOS declared
Muted
1
0
Active Low. Optical signal presence
indicated by SDEXT logic 0 input from
optical module.
High
LOS declared
Muted
1
Active High. Optical signal presence
indicated by SDEXT logic 1 input from
optical module.
Low
Normal
Operation
DLOSDIS
(Internal) DLOS Detect
(External) SDEXT
LOS Declaration
POL
and
Recovered Data Mute
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