參數(shù)資料
型號: XRT91L34IV
廠商: Exar Corporation
文件頁數(shù): 5/38頁
文件大小: 0K
描述: IC MULTIRATE CDR QUAD 128LQFP
標(biāo)準(zhǔn)包裝: 72
類型: 時鐘和數(shù)據(jù)恢復(fù)(CDR),扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: SONET/SDH,STS,STM
輸入: LVDS,LVPECL
輸出: LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
XRT91L34
13
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
1.3
Reference Clock Input
The XRT91L34 can accept either a 19.44 MHz or 77.76 MHz Differential clock input at REFCLKP/N or a
Single-Ended LVTTL clock input at TTLREFCLK. The REFCLKP/N or TTLREFCLK should be generated from
a source which has a frequency accuracy better than ±100ppm in order for the CDR Loss of Lock detector to
have the necessary accuracy required for SONET systems. The reference clock can be provided with one of
two frequencies chosen by CDRREFSEL. The reference frequency options for the XRT91L34 are listed in
Table 2. Figure 3 illustrate the reference clock design options.
TABLE 2: CDR REFERENCE FREQUENCY OPTIONS (LVDS/ DIFF LVPECL OR SINGLE-ENDED LVTTL/LVCMOS)
CDRREFSEL
REFCLKP/N OR TTLREFCLK
FREQUENCY
CHANNEL 0 - 3
AVAILABLE DATA RATES
0
77.76 MHz
STS-1/STM-0 51.84 Mbps
STS-3/STM-1 155.52 Mbps
STS-12/STM-4 622.08 Mbps
1
19.44 MHz
FIGURE 3. REFERENCE CLOCK DESIGN OPTIONS
Single-Ended LVTTL/LVCMOS
Reference Clock Option
Differential LVPECL or LVDS
Reference Clock Option
XRT91L34
130 Ohm
REFCLKP and REFCLKN pins
internally biased and terminated with
100 Ohm line-to-line
Tie unused TTLREFCLK
input pin to GND
Differential Clock
Source
77.76/19.44 MHz
TTLREFCLK
XRT91L34
Leave REFCLKP unconnected
and
tie REFCLKN pin to GND
Single Ended
Clock Source
77.76/19.44 MHz
Resistors for LVPECL
Remove for LVDS
REFCLKP
REFCLKN
VBB1.2
100
Internal
REFCLK
VBB1.2
100
Internal
REFCLK
REFCLKP
REFCLKN
TTLREFCLK
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