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參數(shù)資料
| 型號： | XRT91L81IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PBGA196 |
| 封裝： | 12 X 12 MM, STBGA-196 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大小： | 264K |
| 代理商： | XRT91L81IB |
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XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
20
3.7
Two types of loop timing are possible in the XRT91L81. In the regular loop timing mode (without an external
VCXO), the loop timing is controlled by the LPTIME_NO_JA pin. This mode is selected by asserting the
LPTIME_NO_JA signal to a high level. When the loop timing mode is activated the external reference clock to
the input of the CMU is replaced with the 1/16th or the 1/32nd of the high-speed recovered receive clock from
the CDR. Under this condition both the transmit and receive sections are synchronized to the recovered
receive clock. The normal looptime mode directly locks the CMU to the recovered receive clock with no
external de-jittering.
In cases when the jitter of the recovered receive clock does not satisfy the strict ITU and Bellcore jitter
generation requirements, an external VCXO-based PLL can be used to clean up the jitter of the recovered
receive clock. In this case the VCXO_SEL pin should be set high. By doing so, the CMU receives its reference
clock signal from an external VCXO connected to the VCXO_INP/N inputs. The LPTIME_JA pin must also be
set high in order to select the recovered receive clock as the reference source for the de-jitter PLL. In this state,
the VCXO will be phase locked to the recovered receive clock through a narrowband loop filter. The use of the
on-chip phase/frequency detector with charge pump and an external VCXO to remove the transmit jitter due to
jitter in the recovered clock is shown in Figure 10. The on-chip phase/frequency detector can also be used to
remove the jitter from a noisy reference signal that is applied to the REFCLKP/N inputs. In this case the
LPTIME_NO_JA pin should be set "Low", the VCXO_SEL set "High", and the LPTIME_JA pin set "Low". In this
configuration, the REFCLKP/N signal is used as the reference to the de-jitter PLL and the de-jittered output of
the phase locked VCXO is used as the timing reference to the CMU. Table 5 provides configuration for
selecting the loop timing and reference de-jitter modes.
Loop Timing and clock control
T
ABLE
5: L
OOP
TIMING
AND
REFERENCE
DE
-
JITTER
CONFIGURATIONS
VCXO_SEL
LPTIME_JA
LPTIME_NO_JA
A
CTION
0
0
0
Normal mode
0
0
1
Loop timing without de-jitter
1
0
0
Reference de-jitter
1
1
0
Loop timing with de-jitter
相關(guān)PDF資料 |
PDF描述 |
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| XRT91L82 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82IB | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT94L31_07 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER |
| XRT94L31IB | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L82 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT94L31 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
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