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參數(shù)資料
| 型號(hào)： | XRT91L81IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PBGA196 |
| 封裝： | 12 X 12 MM, STBGA-196 |
| 文件頁(yè)數(shù)： | 35/40頁(yè) |
| 文件大?。?/td> | 264K |
| 代理商： | XRT91L81IB |
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XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
REV. P1.0.3
33
T
ABLE
11: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
C
HANNEL
0 C
ONTROL
R
EGISTER
(0
X
04
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
X
D6
POLARITY
Polarity for LOS Input Select
LOSEXT and POLARITY bits will be Exlussive NORed
internally to generate the correct polarity.
R/W
0
D5
LOOPTM_JA
Loop Timing With JA
The LOOPTM_JA bit must be set to "1" in order to select the recov-
ered receive clock as the reference source for the de-jitter PLL.
"0" = Disabled
"1" = Enabled
R/W
0
D4
LPTIMJADIS
Loop Timing With No JA
When the loop timing mode is activated the external reference
clock to the input of the CMU is replaced with the 1/16th or the 1/
32nd of the high-speed recovered receive clock from the CDR.
"0" = Disabled
"1" = Loop timing Activated
R/W
0
D3
DISRD
Receive Output Disable Upon LOS
If this bit is set to "1", the receive output data will automically pull
"Low" when a LOS condition occurs.
"0" = Disabled
"1" = Mute Data Upon LOS
R/W
0
D2
TRIRXD
Receive Output Tri-State
This bit is used to control the activity of the 4-bit parallel receive
output bus and its reference clock.
"0" = Normal Mode
"1" = Tri-State RXDP/N[3:0] and RXCLK
R/W
0
D1
RXSEL
Receive Serial Input Select
This bit is used to select the Receive Serial Data Input from the pri-
mary or secondary inputs.
"0" = RXI0
"1" = RXI1
R/W
0
D0
VCXOLKEN
De-Jitter PLL Lock Detect Enable
This bit enables the VCXO lock detect Pin N8 to be active.
"0" = VCXO_LOCK disabled
"1" = VCXO_LOCK enabled
R/W
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT91L82 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82IB | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT94L31_07 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER |
| XRT94L31IB | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L82 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT94L31 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
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