參數(shù)資料
型號： XRT91L81IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： TRANSCEIVER, PBGA196
封裝： 12 X 12 MM, STBGA-196
文件頁數(shù)： 30/40頁
文件大?。?/td> 264K
代理商： XRT91L81IB
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
28
5.2
The serial data input is sampled on the rising edge of SCLK. In readback mode, the serial data output is
updated on the falling edge of SCLK. The serial data must be applied to the transceiver LSB first. The 16 bits
of serial data are described below.
5.2.1
R/W (SCLK1)
The first serial bit applied to the transceiver informs the microprocessor that a Read or Write operation is
desired. If the R/W bit is set to “0”, the microprocessor is configured for a Write operation. If the R/W bit is set
to “1”, the microprocessor is configured for a Read operation.
5.2.2
A[5:0] (SCLK2 - SCLK7)
The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0
(LSB) must be sent to the transceiver first followed by A1 and so forth until all 6 address bits have been
sampled by SCLK.
5.2.3
X (Dummy Bit SCLK8)
The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data if
the readback mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold
either “0” or “1” during both Read and Write operations.
5.2.4
D[7:0] (SCLK9 - SCLK16)
The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the ad-
dress bits. D0 (LSB) must be sent to the transceiver first followed by D1 and so forth until all 8 data bits have
been sampled by SCLK. Once 16 SCLK cycles have been complete, the transceiver holds the data until CS is
pulled “High” whereby, the serial microprocessor latches the data into the selected internal register.
5.3
8-B
IT
S
ERIAL
D
ATA
O
UTPUT
D
ESCRIPTION
The serial data output is updated on the falling edge of SCLK9 - SCLK16 if R/W is set to “1”. D0 (LSB) is pro-
vided on SCLK9 to the SDO pin first followed by D1 and so forth until all 8 data bits have been updated. The
SDO pin allows the user to read the contents stored in individual registers by providing the desired address on
the SDI pin during the Read cycle.
16-B
IT
S
ERIAL
D
ATA
I
NPUT
D
ESCRITPTION
相關(guān)PDF資料
PDF描述
XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT94L31_07 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
XRT94L31IB 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L82 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT94L31 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
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