參數(shù)資料
型號(hào): XRT94L31_07
廠商: Exar Corporation
英文描述: 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
中文描述: 3通道DS3/E3/STS-1給STS-3/STM-1映射器集成電路
文件頁(yè)數(shù): 112/133頁(yè)
文件大?。?/td> 1014K
代理商: XRT94L31_07
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XRT94L31
112
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
1.3.5
Ingress Timing for STS-1/STM-0 Applications
Table 13
presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
Ingress Direction) for STS-1/STM-0 Applications and when the Receive STS-1 TOH Processor block has been
configured to sample the DS3/E3/STS_1_DATA_IN signal upon the
rising edge
of DS3/E3/
STS_1_CLOCK_IN.
Table 14
presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
Ingress Direction) for STS-1/STM-0 Applications and when the Receive STS-1 TOH Processor block has been
configured to sample the DS3/E3/STS_1_DATA_IN signal upon the
falling edge
of DS3/E3/
STS_1_CLOCK_IN.
1.3.6
The Egress DS3/E3/STS-1 Interface Timing
The user should be aware of the followings things about the Egress DS3/E3/STS-1 Interface timing.
a.
If a given channel is configured to operate in the DS3/E3 Mode, then the DS3/E3 Framer block can be
configured to output the outbound DS3/E3 data (via the DS3/E3/STS_1_DATA_OUT and DS3/E3/
STS_1_NEG_OUT output pins) upon either the rising or falling edge of DS3/E3/STS_1_CLOCK_OUT.
If a given channel is configured to operate in the STS-1/STM-0 Mode, then the Transmit STS-1 TOH
Processor block will be operating in the Single-Rail Mode (e.g., the Transmit STS-1 TOH Processor block
will output all outbound STS-1/STM-0 data via the DS3/E3/STS_1_DATA_OUT output pin. No data will be
output via the DS3/E3/STS_1_NEG_OUT output pin).
Further, if a given channel is configured to operate in the STS-1/STM-0 Mode, then the Transmit STS-1
TOH Processor block can be configured to output the outbound STS-1/STM-0 data (via the DS3/E3/
STS_1_DATA_OUT pin) either upon the rising or falling edge of DS3/E3/STS_1_CLOCK_OUT.
b.
c.
The Timing Diagram for the Egress DS3/E3/STS-1 Interface is presented below in
Figure 17
.
T
ABLE
13: T
IMING
I
NFORMATION
FOR
THE
I
NGRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
STS-1/STM-0
A
PPLICATIONS
(
RISING
EDGE
OF
DS3/E3/STS_1_CLOCK_IN)
S
YMBOL
D
ESCRIPTION
M
IN
.
T
YP
.
M
AX
.
t9
DS3/E3/STS_1_DATA_IN to rising edge of DS3/E3/STS_1_CLOCK_IN
set-up time requirements
4ns
t10
Rising edge of DS3/E3/STS_1_CLK_IN to DS3/E3/STS_1_DATA_IN and
DS3/E3/STS_1_CLOCK_IN Hold time requirements
0ns
T
ABLE
14: T
IMING
I
NFORMATION
FOR
THE
I
NGRESS
DS3/E3/STS-1 LIU I
NTERFACE
FOR
STS-1/STM-0
A
PPLICATIONS
(
FALLING
EDGE
OF
DS3/E3/STS_1_CLOCK_IN)
S
YMBOL
D
ESCRIPTION
M
IN
.
T
YP
.
M
AX
.
t9
DS3/E3/STS_1_DATA_IN to falling edge of DS3/E3/STS_1_CLOCK_IN
set-up time requirements
4ns
t10
Falling edge of DS3/E3/STS_1_CLK_IN to DS3/E3/STS_1_DATA_IN and
DS3/E3/STS_1_CLOCK_IN Hold time requirements
0ns
相關(guān)PDF資料
PDF描述
XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
XRT94L31IB 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
XRT94L43A SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
XRT94L43 SONET/SDH STS-12/STM-4 TO E3/DS3/STS-1 MAPPER/DEMAPPER
XRT94L43IB SONET/SDH STS-12/STM-4 TO E3/DS3/STS-1 MAPPER/DEMAPPER
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