XRT94L31
34
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
AF19
AG21
AE17
STUFFCNTL_0/
TXHDLC_CLK_0
STUFFCNTL_1/
TXHDLC_CLK_1
STUFFCNTL_2/
TXHDLC_CLK_2
I/O
TTL/
CMOS
STUFFCNTL_n/TxHDLC_CLK_n:
The function of this input pin depends upon (1) whether or not the
XRT94L31 has been configured to operate in the ATM UNI/PLCP Mode
and (2) whether a given DS3/E3 Framer block/Channel has been config-
ured to operate in the High-Speed HDLC Controller Mode, as described
below.
STUFFCNT_n:Transmit PLCP Processor block Nibble-Stuff Control
Input pin - ATM UNI Mode Only:
This pin only functions in this particular role if the XRT94L31 has been
configured to operate in the ATM UNI Mode.
TxHDLC_CLK[2:0]:Transmit HDLC Controller block Clock output
signal - High-Speed HDLC Controller Mode Only:
This output signal functions as the demand clock for the Transmit HDLC
Controller, associated with the DS3/E3 Framer blocks. Whenever the
user pulls the Snd_Msg input pin "High" then the Transmit HDLC Con-
troller block begins to sample and latch the contents of the TxHDL-
CDat[7:0] input pins upon the falling edge of this clock signal. The user
is advised to configure their terminal equipment circuitry to output (or
place) data onto the TxHDLCDat[7:0] bus upon the rising edge of this
clock signal.
Since the Transmit HDLC Controller block is sampling and latching 8-bits
of data at a given time, it may be assumed that the frequency of the
TxHDLC_CLK_n output signal is either 34.368MHz/8 or 44.736MHz/8.
In general, this presumption is true. However, because the Transmit
HDLC Controller block is also performing Zero-Stuffing of the user data
that it accepts from the Terminal Equipment, the frequency of this signal
may be slower.
N
OTE
:
If the DS3/E3 Framer block has NOT been configured to operate
in the High-Speed HDLC Controller Mode, tie this pin to GND.
AC17
AD17
AG20
EIGHTKHZSYNC_0/
RXHDLC_CLK_0
EIGHTKHZSYNC_1/
RXHDLC_CLK_1
EIGHTKHZSYNC_2/
RXHDLC_CLK_2
I/O
TTL/
CMOS
EIGHTKHZSYNC_n/RXHDLC_CLK_n:
The function of this input pin depends upon (1) whether or not the
XRT94L31 has been configured to operate in the ATM UNI/PLCP Mode
and (2) whether a given DS3/E3 Framer Block/Channel has been config-
ured to operate in the High-Speed HDLC Controller Mode, as described
below.
EIGHTKHZSYNC_n: Transmit PLCP Processor Block 8kHz Framing
Alignment Input - ATM UNI Mode Only:
This pin only functions in this particular role if the XRT94L31 has been
configured to operate in the ATM UNI Mode.
RxHDLC_CLK_n: Receive High-Speed HDLC Controller Output
Interface block - Clock output signal - High-Speed HDLC Controller
over DS3/STS-3 Mode Only:
The Receive High-Speed HDLC Controller Output Interface block out-
puts data via the RxHDLCDat_n[7:0] output pins upon the rising edge of
this clock signal. The user is advised to configure the terminal equip-
ment to sample the contents of the RxHDLCDat_n[7:0] output pins upon
the falling edge of this clock signal.
N
OTE
:
If the DS3/E3 Framer block has NOT been configured to operate
in the High-Speed HDLC Controller Mode, tie this pin to GND.
D27
TXPERR
I
TTL
For Mapper applications, please connect this pin to GND.
G25
TxPEOP
I
TTL
For Mapper applications, please connect this pin to GND.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION