參數(shù)資料
型號: XS1-G02B-FB144-C4
廠商: XMOS
文件頁數(shù): 24/24頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 16KB OTP 144FBGA
標準包裝: 176
系列: XS1
核心處理器: XCore
芯體尺寸: 32 位雙核
速度: 400MHz
連通性: USB
輸入/輸出數(shù): 88
程序存儲器容量: 16KB(4K x 32)
程序存儲器類型: OTP
RAM 容量: 32K x 32
電壓 - 電源 (Vcc/Vdd): 0.95 V ~ 3.6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 144-FBGA
包裝: 托盤
其它名稱: 880-1006
XS1-G02B-FB144 Datasheet
8
5
Product Overview
The XMOS XS1-G02B-FB144 is a powerful device that provides a simple design
process and highly-exible solution to many applications. The device consists of
two XCores, each comprising an event-driven processor with tightly integrated
I/O and on-chip memory. The processors run mutiple tasks simultaneously using
hardware threads, each of which is guaranteed a slice of processing power and
can execute computational code, control software and I/O interfaces. Threads use
channels to exchange data within a core or across cores. The cores are connected
via an integrated switch network, which uses a proprietary physical layer protocol,
and which can also be used to add additional resources to a design. The I/O pins
are driven using intelligent ports that can serialize data, interpret strobe signals
and wait for scheduled times or events, making the device ideal for real-time
control applications.
The device can be congured using a set of software components that are rapidly
customized and composed. XMOS provides source code libraries for many standard
components. The device can be programmed using high-level languages such as
C/C++ and the XMOS-originated XC language. XC provides extensions to C that
simplify the control over concurrency, I/O and time.
The XMOS toolchain includes compilers, a simulator, debugger and static timing
analyzer. The combination of real-time software, a compiler and timing analyzer
enables the programmer to close timings on components of the design without a
detailed understanding of the hardware characteristics.
5.1
Threads, Synchronizers and Locks
Each XCore has up to eight active threads, which issue instructions down a shared
four-stage pipeline. Instructions from the active threads are issued round-robin. If
up to four threads are active, each thread is allocated a quarter of the processing
cycles. If more than four threads are active, each thread is allocated at least
1
/n cycles (for n threads). Figure 1 shows the guaranteed thread performance
depending on the number of threads used.
Speed Grade
Minimum MIPS per thread (for n threads)
1
2
3
4
5
6
7
8
400 MHz
100
80
67
57
50
Figure 1:
Thread
performance
There is no way that the performance of a thread can be reduced below these
predicted levels. Because threads may be delayed on I/O, however, their unused
processor cycles can be taken by other threads. This means that for more than
four threads, the performance of each thread is often higher than the predicted
minimum.
Document Number: 1100C
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