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參數(shù)資料
| 型號： | XWM8711EDS |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Internet Audio DAC with Integrated Headphone Driver |
| 中文描述： | 互聯(lián)網(wǎng)音頻DAC集成耳機驅(qū)動器 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大?。?/td> | 379K |
| 代理商： | XWM8711EDS |
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WM8711
Product Preview
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
28
In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue
circuitry remain active. The active analogue includes the analogue VMID reference so that the
analogue line outputs and headphone outputs remain biased to VMID. This reduces any audible
effects caused by DC glitches when entering or leaving STANDBY mode.
The device can be powered off by writing to the POWEROFF bit of the Power Down register. In
POWEROFF mode the Control Interface and a small portion of the digital remain active. The
analogue VMID reference is disabled. Refer to Table 21.
P
C
O
O
D
L
DESCRIPTION
1
0
0
X
1
1
POWEROFF, but with Crystal Oscillator OS and
CLKOUT available
POWEROFF, but with Crystal Oscillator OS
available, CLKOUT not-available
POWEROFF, Crystal oscillator and CLKOUT
not-available.
1
1
0
X
1
1
1
1
1
X
1
X
Table 21 Poweroff Mode
REGISTER MAP
The complete register map is shown in Table 22. The detailed description can be found in the
relevant text of the device description. There are 8 registers with 9 bits per register. These can be
controlled using either the 2 wire or 3 wire MPU interface.
REGISTER
ADDRESS
0000010
Left Headphone
Out
BIT
LABEL
DEFAULT
DESCRIPTION
6:0
LHPVOL
[6:0]
1111001
( 0dB )
Left Channel Headphone Output
Volume Control
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
Left Channel Zero Cross detect
Enable
1 = Enable
0 = Disable
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
7
LZCEN
1
8
LRHPBOTH
0
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